Question

CS-320 Computer Organization and Architecture Homework #7 Due: 04/15/2019 1. (25 points total) Consider the following loop. LOOP: ld x10, e(x13) ld x11, 8 (x13) add x12, x10, x11 subi x13, x13, 16 bnez x12, LOOP Assume that perfect branch prediction is used (no stalls due to control hazards), that there are no delay slots, that the pipeline has full forwarding support, and that branches are resolved in the EX (as opposed to the ID) stage. (20 points) Show a pipeline execution diagram for the first two iterations of this loop. a. Instr./cc 1 2 (5 points) Mark pipeline stages that do not perform useful work (you may mark them on the above table, such as ME). b.

Answer 1

Answer is as follows :

Pipeline Diagram for given scenario is as follows :

	1	2	3	4	5	6	7	8	9	10
Instruction 1	IF	ID	EX	MEM	WB
Instruction 2		IF	ID	EX	MEM	WB
Instruction 3			IF	ID	EX	MEM	WB
Instruction 4				IF	ID	EX	MEM	WB
Instruction 5					IF	ID	EX	MEM	WB

So we need 9 clock cycles for given scenario to execute.

For part b, the stages that are not useful are only with branch instruction, as we know that branch instruction is executed in part EX, so we don't need to go further.

So MEM and WB stages are not useful in instruction 5. Showed by bold in pipeline diagram.

if there is any query please ask in comments...

Answer 2

como se llama ese tema?