1. In VHDL, create a component for each of the operations in table1 and any other components you may need to implement the ALU.
2. Create the top‐level VHDL file that instantiates the components to create the 4‐bit five function ALU
3. Write a self‐checking testbench to exhaustively test your ALU
Part 1 :
library ieee;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
//Creating OR GATE
entity or_21 is
port (a : in STD_LOGIC;
b : in STD_LOGIC;
y: out STD_LOGIC);
end or_21;
architecture Behavioural of or_21 is
begin
y <= a or b;
end Behavioural;
// Creating AND GATE
entity and_21 is
port (a : in STD_LOGIC;
b : in STD_LOGIC;
y: out STD_LOGIC);
end and_21;
architecture Behavioural of and_21 is
begin
y <= a and b;
end Behavioural;
// creating XOR gate
entity xor_21 is
port (a : in STD_LOGIC;
b : in STD_LOGIC;
y: out STD_LOGIC);
end xor_21;
architecture Behavioural of xor_21 is
begin
y <= a xor b;
end Behavioural;
//Creating Shift Right Logical
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
//extra package for shifts
entity right_shift is
end right_shift;
architecture shift of right_shift is
signal r_Shift1 : std_logic_vector(3 downto 0) := "1000";
signal r_Unsigned_R : unsigned(3 downto 0) := "0000";
signal r_Signed_R : unsigned(3 downto 0) := "0000";
begin
process is
begin
r_Unsigned_R <= shift_right(unsigned(r_Shift1), 2);
r_Signed_R <= shift_right(unsigned(r_Shift1), 2);
wait for 100 ns;
end process;
end architecture shift;
-- Creating Shift Right Arithmetic
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
//extra package for shifts
entity right_shift_arith is
end right_shift _arith;
architecture shift_arithmetic of right_shift_arith is
signal r_Shift1 : std_logic_vector(3 downto 0) := "1000";
signal r_Unsigned_R : signed(3 downto 0) := "0000";
signal r_Signed_R : signed(3 downto 0) := "0000";
begin
process is
begin
r_Unsigned_R <= shift_right(signed(r_Shift1), 2);
r_Signed_R <= shift_right(signed(r_Shift1), 2);
wait for 100 ns;
end process;
end architecture shift_arithemetic;
_______________________________________________________________________________
2nd part :
ALU consists AND OR NOT GATES
But we will implement them logically here.
Alu can perform 8 possible logic operation
Control Signals Operations
000 A + B
001 A - B
010 A - 1
011
A + 1
100 A and B
101 A or B
110 not A
111 A xor B
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity alu is
Port ( a : in signed(3 downto 0);
b : in signed(3 downto 0);
con : in STD_LOGIC_VECTOR (2 downto 0);
out : out signed(3 downto 0));
end alu;
architecture Behavioral of alu is
begin
process(a, b, con)
begin
case con is
when "000" =>
out<= a + b; --addition
when "001" =>
out<= a - b; --subtraction
when "010" =>
out <= a - 1; --sub 1
when "011" =>
out<= a + 1; --add 1
when "100" =>
out <= a and b; --AND gate
when "101" =>
out<= a or b; --OR gate
when "110" =>
out <= not a ; --NOT gate
when "111" =>
out <= a xor b; --XOR gate
when others =>
NULL;
end case;
end process;
end Behavioral;
________________________________________________________________________________
3rd Part :
TestBench Code for Testing the ALU :
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
ENTITY Test_alu IS
END Test_alu;
ARCHITECTURE behavior OF Test_alu IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT alu
PORT(
a : IN signed(3 downto 0);
b : IN signed(3 downto 0);
con : IN std_logic_vector(2 downto 0);
out : OUT signed(3 downto 0)
);
END COMPONENT;
--Inputs
signal a : signed(3 downto 0) := (others => '0');
signal b : signed(3 downto 0) := (others => '0');
signal con : std_logic_vector(2 downto 0) := (others => '0');
--Outputs
signal out : signed(3 downto 0);
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: alu PORT MAP (
a => a,
b => b,
con => con,
out => out
);
-- Stimulus process
proc: process
begin
wait for 100 ns;
a <= "1001";
b <= "1111";
con<= "000";
wait for 100 ns;
con<= "001";
wait for 100 ns;
con<= "010";
wait for 100 ns;
con<= "011";
wait for 100 ns;
con<= "100";
wait for 100 ns;
con<= "101";
wait for 100 ns;
con<= "110";
wait for 100 ns;
con <= "111";
end process;
END;
1. In VHDL, create a component for each of the operations in table1 and any other...
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