Question

FIRST ACTIVITY: (100/100) . SIMPLE 4-BIT ARITHMETIC LOGIC UNIT (ALU): This circuit selects between arithmetic (absolute value, addition) and logical (XOR, AND) operations. Only one result (hexadecimal value) can be shown on the 7-segment display This is selected by the input sel (1..0) B A-BI A+B A xnor B A nand B Input EN: If EN-1result appears on the 7 segment display. If EN=0 → all LEDs in the 7 segment display are off Arithmetic operations: The 4-bit inputs A and B are treated as unsigned numbers. v A+ B: If there is a carry out, ignore it. A-BI: 4-bit result, since IA-BIE [0,15] Tip: zero-extend the inputs to 5 bits and implement A-B (5-bit signed result). Then, implement A-BI, where the 5-bit signed result is always positive. Finally, use the magnitude (4 LSBs) as the unsigned output. Logic Operations (A xnor B, A nand B): HEX to 7 segments DECODER EN These are bit-wise operations. Nexys-4 DDR: Each 7-segment display has active-low inputs (CA-CG) and an active-low enable 'AN'. Make sure that only one 7-segment display is activated (e.g.: ANO 0, AN1-AN7-1 to only use the right-most 7-segment display). Create a new ISE Project. Select the XC7A100T-1CSG324 Artix-7 FPGA device. Write the VHDL code for the given circuit. IMPORTANT: For A+B and A-BI circuits, you must use full adders and logic gates o To implement the Bus MUX and decoder, it is strongly advised that you use the VHDL concurrent statements. To implement the top file, use the Structural Description: Create a separate file for the Arithmetic and Logic circuits, the 4-to-1 Bus MUX, and the Hex to 7-segment decoder Write the VHDL testbench to test the circuit to test r Perform I/O Assignment: Create the UCF file. Nexys-4: Use SWO to Sw7 for the inputs A and B, SW8 to SW10 for the inputs sel and EN, CA-CG (7-segment display signals) for the 7-bit output, and AN7-ANO (anode enable for each 7-segment display) Generate and download the bitstream on the FPGA and test. Demonstrate this to your TA. cases (or all cases) and Timing Simulation of your design. Demonstrate this to your TA ν' . Submit (as a zip file) all the generated files: VHDL code files, VHDL testbench, and UCF file to Moodle (an assignment wil be created). DO NOT submit the whole ISE Project.

Answer 1

This il salechs ben ar thmelic and togic operHons. o one Ksult un be shown on the 1- sestmend ddisplar vse IEEE.STD LobiFC.1164:ALL se工EEE . NUMERIC- STD ALL; enf alu is port Cin/-a : signed (3 elowa k o): oul - alu : out signed (3 clocon oo be 91 process (inp-a , m P-bi setỷ Ou add η

olgale OU da lhen others-> NULL , end ccase end process, end 6ehdviorel, Thest bench VHDL code li ALU VSE leee std -lo yst ieee numeric - std ALL, END Tbdlu

Tb_dluZS 月RCHI TECTURE behav iousoF Component Detlorcution lor the unit under Test cUUT) component au PORT END Com ponen;