Question

The Arithmetic Logic Unit

The first topic for the project is to create an Arithmetic Logic Unit, using a structured approached with a Virtual Hardware Design Language such as Verilog. Mainly, the program is very close to a simulator for a programming calculator.

An ALU typically has the following operations

Math Functions: Add, Subtract, Multiply, Divide, Modulus

Logic Functions: And, Or, XOR, Not, Nand, Nor, XNOR

Error Modes: Divide by Zero, Overflow

Support Functions: No Operation, Shift Left, Shift Right, Reset

And has the following additional abilities

To store the first input

To store the second input

To store the results of the operation

And to use the results of the operation to be one of the inputs.

Addition, subtraction, multiplication for basic math are typical. Long division and modulus for more of a challenge. In addition, an ALU can shift a binary value left or right, with or without a ring behavior. And ALU can have an error state on an overflow or a divide by zero error. And that means an ALU would also have a reset or clear command. And importantly, an ALU can be at rest, with a “no-operation.” The data can be integer, or may include floating point, and can use various methods of sign. It is recommended that an ALU should operate on at least 16-bit integers. And that means the result of an operations should have room for at least 32 bits. That being said, the ALU should have at least ten “modes”, that is operations, and error states, and supporting functions.

Answer 1

ALU refers to Arithmetic and logical unit which is used to perform the operation of mathematical and logical such as addition,substraction,multilpication,division,modulus division ,AND,OR,XOR and XNOR etc.

Program:

module alu(

input [ 7:0] A,B,

input [3:0] ALU_Sel,

output [7:0] ALU_Out,

output CarryOut

);

reg [7:0] ALU_Result;

wire [8:0] tmp;

assign ALU_Out = ALU_Result;

assign tmp = {1'b0,A} + {1'b0,B};

assign_CarryOut = tmp[8];

always @(*)

begin

case(ALU_Sel)

4'b0000:

ALU_Result = A + B;

4'b0001:

ALU_Result = A - B;

4'b0010:

ALU_Result = A * B;

4'b0011:

ALU_Result = A/B;

4'b0100:

ALU_Result = A<<1;

4'b0101:

ALU_Result = A>>1;

4'b0110:

ALU_Result ={ A[6:0],A[7]};

4'b0111:

ALU_Result ={ A[0],A[7:1]};

4'b1000:

ALU_Result = A & B;

4'b1001:

ALU_Result = A | B;

4'b1010:

ALU_Result = A ^ B;

4'b1011:

ALU_Result = ~(A | B);

4'b1100:

ALU_Result = ~(A & B);

4'b1101:

ALU_Result = ~(A ^ B);

4'b1110:

ALU_Result = ~(A > B)?8'd1:8'd0;

4'b1111:

ALU_Result = (A == B)?8'd1:8'd0;

default: ALU_Result = A + B;

endcase

end

endmodule