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Implement an arithmetic logic unit (ALU) using Verilog. Consider signed number arithmetic operation. The outputs of...

Implement an arithmetic logic unit (ALU) using Verilog. Consider signed number arithmetic operation. The outputs of the ALU should be 1) Addition of two 8-bit numbers 2) A Zero Flag. It is set (it is 1 if the condition is met and 0 otherwise) if the result is zero. 3) A Negative Flag. It is set (it is 1 if the condition is met and 0 otherwise) if the result is less than 0. 4) An Overflow Flag. It is set (it is 1 if the condition is met and 0 otherwise) if the result is more than the bit length of the output. 5) A carry flag. It is set (it is 1 if the condition is met and 0 otherwise) when the carry is generated. If the number is unsigned, will there be a need of both carry and overflow flag? To get a clear idea of when carry and an overflow is generated solve the following cases for an 8 bit signed number. Determine if there is a carry output or/and will it overflow. 1. 100+49. 2. -2-1 3. 51+28 4. 126-64

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