Question

1. Design the circuits in Figs. 6(a) and 6(b) with the following specifications NPN PNP 1mA 3.5V 1mA 1.5V VR VEE0 ЕЕ ЕЕ 100 25mV 100 25mV supply 2mA supply 2mA For both circuits, DC biasing should be insensitive to variations in B and |VBel, and lB currents should be designed to be negligible

Answer 1

(a): NPN - transistor: Given Specifications: I_c = 1 mA, V_c = 3.5 V, V_cc greaterthanorequalto IV, V_RE greaterthanorequalto IV, V_ce = 5 V, V_EE = 0V, Beta, V_T = 25 mv, I_supply lessthanorequalto 2 mA - V_cc + I_c R_c + V_c = 0 - 5 + (1 mA) R_c + 3.5 = 0 R_c = 5 - 3.58/1 mA = 1.5 k ohm I_c = alpha I_E Rightarrow I_E = I_e/alpha (Because = Beta/1 + Beta Therefore I_ E = 1.01 mA I_B is negligible (I_B = 0 A) Let Assuming V_CE - 2.5 V