Question

A computer needs to handle any interrupts it receives. The interrupts can be caused by a variety of things (an error or an I/O request, for example). Interrupts are handled on a priority basis, but once an Interrupt is being handled no other Interrupt can be accepted by the microprocessor.

For this circuit, you will need to build a priority encoder which can handle up to 4 Interrupt s (0-3). This encoder will have an enable which will either enable or disable the encoder. Provide your design work for this encoder. The encoder feeds a parallel load register (the one you created for lab 6 is sufficient), which will hold the output of the encoder. Once the register has a value (is no longer 000), no other value can be accepted for a count of 5 regardless of the output of the priority encoder. Once this count has been reached all circuits (register and counter) must be reset and the encoder re-enabled. If you get an error 0, generate a signal called Error_Zero, but do NOT load the register.

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PLEASE SHOW ME THE SPECIFIC GATE BECAUSE I WILL USE IT ON ORCAD.

PLEASE DO NOT SHOW ME A BOX THAT SAID IS A 4 BY 1 MUX.

THANK YOU VERY MUCH.

Answer 1

Truth table of an 4-2 line encoder :

I₃   I₂ I₁ I₀   Y₁ Y₀

_{0 0 0 1 0 0}

_{0 0 1 0 0 1}

_{0 1 0 0 1 0}

_{1 0 0 0 1 1}

_where I₃   I₂ I₁ I_{0 are the inputs to the encoder system and}    Y₁ Y_{0 are the output of the encoder system}

Digital design: