Question

When your design needs a NAND gate, and you only have OR gates and inverters you could use two OR gates connected V Which of the following are real-world considerations in your design, is about the time it takes to travel through a component None of these Static 1 hazard and static O hazards can be fixed in your design by including all corresponding cov When your design requires a multiplexer, you can implement it by using all of these except PoS implemented with "AND' Select NOR gates only ed block tree state buffers PoS implemented with "AND" & "OR" gatest an Encoder only NAND gates only Decoder with "OR" gate(s) smaller MUX(s) n active low SOP implemented with "AND" & "OR" gates enabre te the component will then be enabled when E- (falling edge)

Answer 1

Soln)

on when your design needs a NAND gate, and you only have OR gates and inverters you could use two OR gates connected V Which of the following are real-world considerations in your design, is about the time it takes to travel through a component None of these 3 Static 1 hazard and static O hazards can be fixed in your design by including all corresponding ca Y When your design requires a multiplexer, you can implement it by using all of these except PoS implemented with "AND' Select] NOR gates only ed block tree state buffers PoS implemented with "AND" & "OR" gates an Encoder only NAND gates only Decoder with "OR" gate(s) smaller MUX(s) n active low SoP implemented with "AND" & "OR" gates enabre TEJ the component Wirthen be enabled when E- (falling edge) When a component in your design has an active low enable (E) the component will then be enabled when E- (falling edge) Select E-1 E-X E 1 (rising edge) None of these E-0 Fl falling deel

A Do y= AB B Nand gate Demorgan's 's Law - AB A + = A-10 ya à TB = AB B-Da Nand gate 1 OR crate + 2 inverter / Ang 2) signal takes time to travel through a component known as Delay-provide by the component / Latency Any 3) Static 1 hazard and Static o hazard can be fixed by adding redundant Logic, consensus terms in the logic expression. Any consensus theorem - AB+ ÃC ABC = ABTĀC 1 redundant term u ) A MUX 2:1 y=(50 A +506) B so 2 То Il I 2 2:2 Encoder Yo YI Iz EN = MUX Encoder +OR) = we can't made mux by using encoder only. Encoder only Any 5) Yo Active Low enable E when E=0 component will be enable. Ary