Question

how slove 4-34, 4-35, 4-36??? I dont know that! please hlep me!

306 □ CHAPTER 4/SEQUENTIAL CIRCUITS OTABLE 4-16 State Table for Problem 4-33 Next State Input Output Present State 4-36 4-37 0 0 0 0 4-38 Design the circuit specified by Table 4-14 and use the sequence from Problen 4-31 (either yours or the one posted on the text website) to perform an automatic logic simulation-based verification of your design. 4 433. The state table for a sequential circuit is given in Table 4-16 4-3 (a) Draw the state diagram for the circuit (b) Implement the circuit using D ftip-topsand minima input functions for each flip-flop. Reset is asynchronous and active low (RESET), and each flp-lop. Kesetis asynchronous andactive low (RESET ),and initializesThe state-to A. 0,B O. 4-34) Design a negative-edge-triggered lip-flop. The flip flop has three inputs; these are Data, Clock, and Enable. If, at the negative edge of the clock,the enable input equals to 0, then the state at Data input is stored in the flip-flop.I, at the negative edge of clock, Enable is in 1 state, then the current stored value in the flip-flop is held. Design the flip-flop using only SR latches, AND gates and NOT gates. 35 Find a state-machine diagram, that is equivalent to the state diagram s as much as Figure 4-55. Reduce the complexity of the transition condition possible. Attempt to make outputs unconditional by changing Mealy to Moore outputs. Make a state assignment to your state-machine di Reset 10/0, 11/0 01/1, 11/0 00/0,01/1 Output z. 01/1, 101 00/0, 01/0 00/1,10/0 00/1, 11/1 10/0, 11/1 O FIGURE 4-55 State Diagram for Problem 4-35 Problems 307 and find an implementation for the corresponding sequential circuit using D op-ilops,AND gates, OR gates, and inyerters. Design the sequential circuit for the state-machine diagram from Problem 36 4-35. Use a one-hot state assignment, D flip-flops and AND gates, OR gates and inverters. 4-37. (a) Verify that the transitions in the state-machine diagram in Figure 4-27 bey the two transition conditions for state diagrams. (b) Repeat part (a) for the state-machine diagram in Figure 4-28 4-38. *You are to find the state-machine diagram for the following electronic vending-machine specification.The vending machine sells jawbreaker candy, one jawbreaker for 25c. The machine accepts N (nickels 5c), D (dimes 10c), and Q (quarters 25c). When the sum of the coins inserted in sequence is 25t or more, the machine dispenses one jawbreaker by making DJ equal to 1 and returns to its initial state. No change is returned DJ equals 0 for all other stat If anything less than 25c is inserted and the CR (Coin Return) pushbutton is pushed, then the coins deposited are returned through the coin return slot by making RC equal to 1, after which the machine returns to its initial state. R equals 0 in all other states. Use Moore outputs for your design. from Problem o perform an 4-39. You are to find the state-machine diagram for the following electroni vending-machine specification. The vending machine sells soda for $1.50 per bottle. The machine accepts only D ($1 bills) and Q (quarters 25c). When the sum of money is greater than $1.50, i.e., two $1 bills, the machine returns change in the coin return (two quarters). When $1.50 has been paid, the machine lights an LED to indicate that a soda flavor may be selected. The choices by pushbutton are C (Cola), L (Lemon soda), O (Orange soda), and R (Root Beer). When one pushbutton is pushed, the selected soda is dispensed and the machine returns to its initial state. One other feature is that unctions for an e inputs; these ck, the enable -flop. If, at the tored value in an LED comes on to warn the user that two quarters are not available for change, so if a second $1 bill is inserted, no change will be given ND gates, and (a) Find the state-machine diagram for the soda vending machine as specified. te diagram in ns as much as (b) The specification as given is not very user friendly. Rewrite it to provide a remedy for every possible situation that the user might encounter in using the machine. Mealy outputs chine diagram All files referred to in the remaining problems are available in ASCII fornm for simulation and editing on the Companion Website for the text. A VHDL or Verilog compiler/simulator is necessary for the problems or portions of problems requesting simulation. Descriptions can still be written, however tor many of the problems without using compilation or simulation 4-40, Write a gate-level structural VHDL description for the circuit from Problem . Use the 4-11. Use the VHDL model for a D flip-flop from Figure 4-29 package func_prims in library 1cdf_vhdl for the logic gate components 01/1, 10/1 306 □ CHAPTER 4/SEQUENTIAL CIRCUITS OTABLE 4-16 State Table for Problem 4-33 Next State Input Output Present State 4-36 4-37 0 0 0 0 4-38 Design the circuit specified by Table 4-14 and use the sequence from Problen 4-31 (either yours or the one posted on the text website) to perform an automatic logic simulation-based verification of your design. 4 433. The state table for a sequential circuit is given in Table 4-16 4-3 (a) Draw the state diagram for the circuit (b) Implement the circuit using D ftip-topsand minima input functions for each flip-flop. Reset is asynchronous and active low (RESET), and each flp-lop. Kesetis asynchronous andactive low (RESET ),and initializesThe state-to A. 0,B O. 4-34) Design a negative-edge-triggered lip-flop. The flip flop has three inputs; these are Data, Clock, and Enable. If, at the negative edge of the clock,the enable input equals to 0, then the state at Data input is stored in the flip-flop.I, at the negative edge of clock, Enable is in 1 state, then the current stored value in the flip-flop is held. Design the flip-flop using only SR latches, AND gates and NOT gates. 35 Find a state-machine diagram, that is equivalent to the state diagram s as much as Figure 4-55. Reduce the complexity of the transition condition possible. Attempt to make outputs unconditional by changing Mealy to Moore outputs. Make a state assignment to your state-machine di Reset 10/0, 11/0 01/1, 11/0 00/0,01/1 Output z. 01/1, 101 00/0, 01/0 00/1,10/0 00/1, 11/1 10/0, 11/1 O FIGURE 4-55 State Diagram for Problem 4-35

Answer 1

4-35)

State cdiagram Inputs:XY Output: z YIZ XYXY State table: Transitions of A: From the state diagram, for the input values of X and Y are 00 and 01, state of A cant be changed and output is 0, The transition condition for A is 00-X Y ' 01 = XY, is common for both). Therefore, the next state is A with zero output For the input values 10 and 11, A changes its state to B. The transition condition for A is X10 =X Ỹ , 11 =XY. X is common for both). Therefore, the next state is B with zero output. Transitions of B: For the input values 00 and 10, B changes its state to A. The transition condition for B is y (00 ▼ , 10-x Ỹ , ▼ is common for both) · Therefore, the next state is A with zero output for 00 and output 1 for 10 ·For the input values 01 and 11, B changes its state to C. The transition condition for B is Y (01 = XY 11EXY, Y is common for both). Therefore, the next state is C with zero output for 11 and output 1 for 01 Transitions of C: For the input values 00 and 01, C changes its state to D. The transition condition for C is = Ỹ . 0 1 XY, X is common for both) (00 Therefore, the next state is D with zero output for 00 and output 1 for 01 For the input values 10 and 11, C changes its state to A. The transition condition for C is X (10 =X ▼ 11-X. X is common for both) Therefore, the next state is A with zero output for 10 and output 1 for 11 Transitions of D:

. For the input values 00 and 11, D changes its state to C. The transition condition for D is xY+XY (there are no common inputs) Therefore, the next state is C with output 1 for both the inputs. . For the input values 01 and 10, D's state remains same. The transition condition for D is XY XY (there are no common inputs) Thercfore, the ncxt statc is D with output 1 for both thc inputs. The state table below shows that, the next states and non-zero outputs. State State code Transition Next state State code Non-zero outputs 10 10 YiZ 10 Sequential circuit for the state table is shown below: RESET Y2