Question

Its logic design

my sequence is 127605

i need help with all this pages please and thank you

27 60 Experiment 4 Six-State Up-Down Counter 1 Objective To become familiar with the design procedures of a counter, which are applicable to the design of other synchronous sequential circuits. 2 Problem description A six-state up-down counter is to be designed. Three flip-flops with outputs Q2,Qi and Qo are required in the design. As shown in Figure 1, the counter is initialized by applying a positive pulse to the RESET input of the counter. The initialization places the circuit in the initial state So where the normal counter sequence starts. Note that the RESET input is 0 during normal counting operation. The direction of counting depends on a control signal C. When C 0, the circuit is an up-counter. The counting sequence is reversed if C-1. RES S2) So S3 S4 Ss State diagram for a 6-state up-down counter. Figure 1 Two designs are required: one using D-type flip-flops, another using JK-type flip- flops. For each design, follow the procedure listed below (1) Construct a state diagram. (2) Construct a transition table. (3) Convert the transition table to next-state maps. (4) Obtain the excitation functions from the next-state maps. (5) Draw a schematic diagram. The counter sequence assigned to you can be found on pages 19-25. Two ofthe states are unused. If for any reason the circuit strays from the normal cou sequence to an unused state, it must be able to return to sequence. Thus ntin the normal counting the next state for each of the two unused states should be verified, 1260S SF2 Experiment 4 Six-State Up-Down Counter S3.6 1. Sequence assignment 53 2. Next-state maps Present state | Next state Q+2Q+10% 0 0 1 1 0 0 1 1 0 Convert the transition table to next-state maps cQo 00 01 11 10 00 01 11 10 cQo 00 01 11 10 01 01 01 10 10 10 3. Design using D flip-flops 00 01 11 10 C000 11000 01 01 01 10 10 10 Di Determine the excitation functions from the next state maps. Do List of ICs and unused gates for design using D flip-flops Unused gates Function IC number Type number 7474 Dual D type flip-flopsNone 7474 Dual D type flip-flops 1D flip-flop 6 Simulation results for design using D flip-flops C 0 C=1 Unused Unused Design using JK flip-flops 4. 00 01 11 10 00 01 11 10 00 01 11 10 01 01 01 10 10 10 Partition the next state maps into K-maps for the excitation functions. (Don't forget to label the variables at the upper left corner of each K-map.) 00 01 11 10 00 01 11 10 00 01 11 10 J, 00 0 11 10 00 01 11 10 00 01 11 10 Ki Determine the excitation functions from the six K-maps.

Answer 1

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