Homework Answers
TASK 5.1.1
We will individually design UP Counter without overflow and DOWN Counter without underflow.
Later we will logically AND with mode control UP/DOWN switch. If UP/DOWN = 0 then UP Count, UP/DOWN = 1 then DOWN Count.
TRUTH TABLES :
UP COUNTER WITHOUT OVERFLOW USING D FLIP FLOP
|
PRESENT STATE |
NEXT STATE |
||||||
|
Q3 |
Q2 |
Q1 |
Q0 |
Q3+ |
Q2+ |
Q1+ |
Q0+ |
|
0 |
0 |
0 |
0 |
0 |
0 |
0 |
1 |
|
0 |
0 |
0 |
1 |
0 |
0 |
1 |
0 |
|
0 |
0 |
1 |
0 |
0 |
0 |
1 |
1 |
|
0 |
0 |
1 |
1 |
0 |
1 |
0 |
0 |
|
0 |
1 |
0 |
0 |
0 |
1 |
0 |
1 |
|
0 |
1 |
0 |
1 |
0 |
1 |
1 |
0 |
|
0 |
1 |
1 |
0 |
0 |
1 |
1 |
1 |
|
0 |
1 |
1 |
1 |
1 |
0 |
0 |
0 |
|
1 |
0 |
0 |
0 |
1 |
0 |
0 |
1 |
|
1 |
0 |
0 |
1 |
1 |
0 |
1 |
0 |
|
1 |
0 |
1 |
0 |
1 |
0 |
1 |
1 |
|
1 |
0 |
1 |
1 |
1 |
1 |
0 |
0 |
|
1 |
1 |
0 |
0 |
1 |
1 |
0 |
1 |
|
1 |
1 |
0 |
1 |
1 |
1 |
1 |
0 |
|
1 |
1 |
1 |
0 |
1 |
1 |
1 |
1 |
|
1 |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
DOWN COUNTER WITHOUT UNDERFLOW USING D FLIP FLOP
|
PRESENT STATE |
NEXT STATE |
||||||
|
Q3 |
Q2 |
Q1 |
Q0 |
Q3+ |
Q2+ |
Q1+ |
Q0+ |
|
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
|
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
|
0 |
0 |
1 |
0 |
0 |
0 |
0 |
1 |
|
0 |
0 |
1 |
1 |
0 |
0 |
1 |
0 |
|
0 |
1 |
0 |
0 |
0 |
0 |
1 |
1 |
|
0 |
1 |
0 |
1 |
0 |
1 |
0 |
0 |
|
0 |
1 |
1 |
0 |
0 |
1 |
0 |
1 |
|
0 |
1 |
1 |
1 |
0 |
1 |
1 |
0 |
|
1 |
0 |
0 |
0 |
0 |
1 |
1 |
1 |
|
1 |
0 |
0 |
1 |
1 |
0 |
0 |
0 |
|
1 |
0 |
1 |
0 |
1 |
0 |
0 |
1 |
|
1 |
0 |
1 |
1 |
1 |
0 |
1 |
0 |
|
1 |
1 |
0 |
0 |
1 |
0 |
1 |
1 |
|
1 |
1 |
0 |
1 |
1 |
1 |
0 |
0 |
|
1 |
1 |
1 |
0 |
1 |
1 |
0 |
1 |
|
1 |
1 |
1 |
1 |
1 |
1 |
1 |
0 |
Karnaugh Map:
![UP COUNTER 1 1 10 00 01 01 11 10 83D3=3+Q21R0 9D2-R2+o] R3QR0+ RIRO 2342 01 00 10 00 1 0 1 01 1 1 10 4T D2=(R)+ 상= Do=Qot Q3®](http://img.homeworklib.com/images/4c342434-92c2-44a2-bf88-05cbf2d4e08d.png?x-oss-process=image/resize,w_560)
CIRCUIT DIAGRAM
Add Answer to:
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Its logic design my sequence is 127605 i need help with all this pages please and thank you
Its logic design
my sequence is 127605
i need help with all this pages please and thank you
27 60 Experiment 4 Six-State Up-Down Counter 1 Objective To become familiar with the design procedures of a counter, which are applicable to the design of other synchronous sequential circuits. 2 Problem description A six-state up-down counter is to be designed. Three flip-flops with outputs Q2,Qi and Qo are required in the design. As shown in Figure 1, the counter is initialized...
how slove 4-34, 4-35, 4-36??? I dont know that! please hlep me! 306 □ CHAPTER 4/SEQUENTIAL CIRCUITS OTABLE 4-16...
how slove 4-34, 4-35, 4-36??? I dont know that! please hlep me!
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Design a three-bit counter using D flip-flops that has the following characteristics: When the value of...
Design a three-bit counter using D flip-flops that has the following characteristics: When the value of an input x is 0, the counter counts "down" in standard order. When the value of x is 1, the counter counts "up" in standard order a. First, complete the state table shown below Present State Next State Excitation 0 0 0 0 0 0 1 0 0 0 0 0 0 b. Next, derive the logic equations using the Karnaugh maps shown below...
1) Design a synchronous 3-bit binary UP/DOWN counter uses the following counting pattern 10.2.3.7.6.40.1.3...) the counter will count in this pattern indefinitely when the input X is equal to 1. When the input the counter will reverse direction and count in the opposite pattern 0. 4 7310) Complete the state diagram, transition table, New state s and solve for the recitation equations for flipflops that will perform this function. (You do not need to draw the flip-flops Use the state...
Its logic design
my sequence is 127605
i need help with all this pages please and thank you
27 60 Experiment 4 Six-State Up-Down Counter 1 Objective To become familiar with the design procedures of a counter, which are applicable to the design of other synchronous sequential circuits. 2 Problem description A six-state up-down counter is to be designed. Three flip-flops with outputs Q2,Qi and Qo are required in the design. As shown in Figure 1, the counter is initialized...
how slove 4-34, 4-35, 4-36??? I dont know that! please hlep me!
306 □ CHAPTER 4/SEQUENTIAL CIRCUITS OTABLE 4-16 State Table for Problem 4-33 Next State Input Output Present State 4-36 4-37 0 0 0 0 4-38 Design the circuit specified by Table 4-14 and use the sequence from Problen 4-31 (either yours or the one posted on the text website) to perform an automatic logic simulation-based verification of your design. 4 433. The state table for a sequential circuit...
Design (and then verify your design by simulating it) a two-bit
counter that counts up or down. Use an enable input E to determine
whether the counter is on or off: if E = 0 the counter is disabled
and remains at its present count even if clock pulses are applied.
If E = 1, the counter is enabled and a second input, x, determines
the direction of the count: if x = 1 the circuit counts upward 00,
01,...
The task is to design a two-bit controlled counter which has two
counting bits (Q2, Q1), has one control input C1, and also two
extra outputs, one indicating overflow, the other underflow.
When C1=0 the counter counts up by 2s; i.e. 0 becomes 2, 1
becomes 3. In this mode the values 2 and 3 go to the overflow
state. When the control input C1=1, the counter counts down by 2s,
i.e. 3 becomes 1, and 2 becomes 0, and...
It is a question about Computer organization
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