Question

Up-Down counter with enable using JK flip-flops: Design, construct and test a 2-bit counter that counts up or down. An enable input E determines whether the counter is on or off. If E = 0, the counter is disabled and remains in the present count even though clock pulses are applied to the flip-flops. If E= 1, the counter in enabled and a second input, x, determines the count direction. If x= 1, the circuit counts up with the sequence 00, 01, 10, 11 and the counter repeats. If x = 0, the circuit counts down with the sequence 11, 10, 01, 00 and the counter repeats. Do no use E to disable the clock. Design the sequential circuit with E and x as input.

Answer 1

The design:

when j-k are both set to 1 the j-k flip flop behaves as a t-flip flop

when 00 it holds the current state:

enable is taken as an input and given to both j-k flip flop when en=0 the circuit will not count and will stay in current state

when enable=1 it will count up or down on the choice of input X

the input x determines the count up or down

when counting up in an async. counter Qbar of the previous stage is connected to the clock.

when counting down Q is connected to the clk of the nexstate of the clock

this design can be implemented using a 2:1 mux

the final design is ,