Question

Design a 3 bits binary counter that count up from 000 to 111 and recycles according to the following specification: E is the enable input, if E-0 the counter is disabled and remains in its current state even though clock pulses are applied to the flip-flops. And if E-1 the counter is enabled and count upward with the sequence 000,001,010,011,100,101,110, 111 The second input S is the reset if s-1 the counter is reset to the 000 state, is S-o the counter depends on the value of E Find the truth table, schematic diagrams, and the type of ICs you will use. Explain the advantages of your design from the "cost, power consumption, No of used ICs, No of used logic gates, etc."

Answer 1

Solution:

Truth Table

Present state	S	E	Next state
d	1	1	000
d	1	0	000
000 - 111	0	0	000-111
000	0	1	001
001	0	1	010
010	0	1	011
011	0	1	100
100	0	1	101
101	0	1	110
110	0	1	111
111	0	1	000

The design is implemented using the Verilog HDL Language

//------------- Code Starts Here --------------//

`timescale 1ns / 1ps

module counter(S,E,clk,count
);
input S,E,clk;
output reg [2:0] count;

always @(posedge clk) begin
if(S==1)
   count<=0;
else begin
           if(!E)
               count<=count;
           else
               count<=count+1;
   end
end
endmodule

//----------------------- END ----------------------//

N.B: Please copy the code save it (in a .v file) and simulate using the VERILOG simulator to have the best results.