Question

 Q2) 4-bit Synchronous Counter

 Using Proteus, design Synchronous 4 bit Up binary counter using JK flip flops (Use 74HC76 JK flipflop). The circuit count from 0000 to 1111, etc.

 Experiment procedure: طريقة اجراء التجربة

 a) Complete the circuit. You can use external gates based on the following conditions:

 o Flipflop A switches every clock.

 o Flipflop B switches when the output of flipflop A=1

 o Flipflop C switches when the outputs of A-B=1

 o Flipflop D switches when the outputs of A=B=C=1

 b) What is the typical feature of Synchronous counter compared to Asynchronous counters?

 Answer:

 c) In the Circuit, why are the inputs of the first flipflop fixed at JA-KA-1

 Answer:

Answer 1

Explanation A)

We need to construct synchronous 4 bit up counter which counts from 0 (0000) to 15 (1111).

Conditions you have mentioned are very useful ans external gate here we are using is AND gate.

As you mentioned in condition 3, flipflop C switches only when A=1 and B=1 which implies we have to use AND gate logic.

Same wgoes with condition 4, flipflop D switches only when A=1, B=1 and C=1 which implies we have to use AND gate logic again.

So we are using 2 AND gates here.

Please find below picture for complete circuit.

4-Bit synchronous Up Counter

Here we can see external clock signal is fed to all flip fliops .

As mentioned earlier, B flip flop switches only when A=1. So the J and K inputs of flip-flop B(FFB) are connected directly to the output QA of flip-flop A.

where as we used AND gates incase of flip flop C (FFC) and flip flop D (FFD). these will generate the required logic for the JK inputs of next stage.

For your understanding here I am attaching wave form diagram of the counter

Explanation B)

The main typical feature in synchronous counter is,here external clock is conected to each flip-flop so that all flip-flops are clocked together simultaneously, which means changes in output in snchronous with the clock signal. hence there wont be any ripple effect which means no propogation delay.

Explanation C)

The J-K inputs of only flip flop A are tied together and connected to HIGH logic''1'' alllowing the filp-flop A (FFA) to toggle on every clock pulse. i.e., toggle mode.

Toggle Mode For J-K flip flop: when J=1 and K=1,then flip flop is said to be in togle mode, which means it will switch the output only one time in every clock cycle from one state to another state.