Question

1. Build the 4-bit synchronous count up counter (using two 74109 Dual J-K F.F and 74LS08 AND IC) shown in Figure 5. LOLLSB) L3(M58) 74L SOBD 74LS08D

Answer 1

Part 1-

P.S means the present state

N.S means the next state of the counter
се, o о о, о, о, о, oooo Ооо | оото О от 1 - 1 0 бгоо - o oo o o o o - x x x x xоо 0 . Nos K, 3, 4, 5, K, J, K, ұ, 9, 8, 9, o oот х ох ох кх о о то x ox тxx оо то x ox x0 TX огоо x 1 x x1 x1 о то хо Ох 18 отто хо \ xxт отгох юo xo TX 1боо | x x x x ) По от xo OX OX IX Тоть до ox 1 x x To1 xo ox XO TX doo x0 1 x x x| llor xo 1 X OXIX Тя о хо хонх х тіптхо xo XO TX ото | о то от 1 боо 0 г 2 х о о тоо 1. то то По | | Гоо се x o

Тут 1 оооо X1 X1 X1 X1

! 101 1/1 med en IN K =D CIN NS *1 kg=QQ,30 I am a Jr Se=9,8 1) Toi K, = Q, QO Kool

A four-bit synchronous "up" counter This flip-flop toggles on every clock pulse This flip-flop toggles only if is "high" This flip-flop toggles only if AND Q, are "high" This flip-flop toggles only if Q, AND Q, AND Q2 are "high"

2 Part cok K, Je No $ J, K, Joko Ke P.S - 6 0.06 0,0,0,0,0,99. 0,99.99. 09. 0001 - - Doll o 0 0 - 10 1 0 0 1 9 - op 0 0 3 0 1 Ą I III 5 11 10 1111 o - - 0 - - 0 O.------0 - - - - - - 0 -

% in part 1 . Decimal value of o/p in part 2 COD while counter o clk /p 273 37 157 121 47 15 Ź 2 18->15 -

Parot qo roantage to They are faster with respect to asynchronous counter as the propogation delay is less. 2)-0 They are less likely to end up in enormous State C4 Oyoy YOO "Disaduantage to as the cer signal at synchronous with clock will no clear the peuticulay state to or when the clock cycle become high. This make exsynchronous counted to wait for one ostate to get C0+ o/R : Part 50 * J and K countey But in will remain in esame estate for synchronouy oup le either oo or I'l asynchronous it will always have to be 11.