Question

5. (7 points) Shown in the following block diagram is a 4-bit up-counter with parallel load, clk Dc BA load clr where clr and load are asynchronous inputsi.e., one of the following operations will be performed “simultaneously" (independently of the clock) when the inputs change values: clr load operations 1 X clear 0 0parallel load 1 up-counting 0 the above block diagram and any logic gates you want to build an offset down-counter to count from QpQcQBQA 0111 0110010 . 0010 and then repeat. Draw the block diagram of the circuit and explain how it works.

Answer 1

→ he have plen cep-counter., to make 't k as a doun- counter we needto wok Complemeut the ututs ng NT gutes -→ we have co eated down Counter Ug;n up counter JJow! , since ne have cly and load au8 asynchs onous inputs we can make use of them. womal countes us Countes CAp Counte 0 -> The cowroter stort, at lill-> then it goes mmedatel → we need to den,gm taoCAaauts second ts yuinp from 000→6000 we have actie high load& actie high chears inputs 1111 →0111

Dg Load cleas Oy when 1111 appears at aepuut, the and gate daces high sigmal to load hich by the way dvads the DcsA inputs ー> 0010 is a bit td cky one Cohen it detects oolo itsendshgh to ciean, which chears counter oooo and Ii detects Ly m detedos and makes o stater → So the Collytingfagmence becomes