Question

Consider the circuit in Figure 1. It is a 4-bit (QQ2Q3) synchronous counter which uses four T-type flip-flops. The counter increases its value on each positive edge of the clock if the Enable signal is asserted. The counter is reset to 0 by setting the Clear signal low. You are to implement an 8-bit counter of this type Enable T Q Clock Clear Figure 1. 4-bit synchronous counter (but you need to implement 8-bit counter in this lab) Specific notes: n You should build a T flip-flop module tfliplfop (tff is a reserved key word, so it cannot be used as module name) first, and then instantiate 8 times to create 8-bit counter with module name conter8 2 Modify the 4 bi bcd to 7 segment display module BCD2LEDS from lab 2 to display 0 to F (instead of 0 to 9 for BCD numbers) with module name hex2seg7. Create two instances of hex2seg7 to display the 8-bit counter state Q7 Q6... Q0 in double hex digits. One hex for Q7-4, and another for Q3-0 3) Use SW for Enable, SW[0] for Clear, KEY[0] for clock. ) The output of left TFF is Qlo] (LSB). s) Counter state Q[7:0] also goes to red led display LEDR [7:0] 6 QI7:0] should go through two 7-seg display so that the output of the 8-bit counter can be display on HEX1 and HEX0 as 00 to FF. The counter is accomplished using the statement: Q prelab: complete the following Verilog code)l Design a submodule 8 bit counter module counter8new(resetn, clk,en, Q); input resetn, clk, en output reg [7:0] Q // always block for 8 bit counter with asynchronous low active reset // and synchronous high active enable always @ (posedge clk, negedge resetn) if Cresetn) //low active /l reset else if (en) //lcount up by 1 else /no change endmodule Design the top module module lab3part2(SW, KEY,LEDR.HEXI, HEXO) input [1:0] SW://SW] as enable, SW[0] as input [0:0] KEY; I/ KEY[O] as clock output reg [6:0] HEXI HEX0; to display 8 bits //(2 hex numbers) on two7 seg display output [7:0] LEDR:/ to display counter state on wire [7:0] Q:intermal signals for counter state assign LEDR-Q:/ optional: to have counter LEDR state on LEDR directly // instantiate 8 bit counter couner8new UO(...); instantiate display module twice hex2seg7 U1..); hex2seg7 U2..);

Answer 1

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