Question

Design C-1 (modulo-10 up-counter): Using the behavioral VHDL coding, create an up-counter to count upward. The up counter has the following control inputs En.reset, CLK. The counting outputs are Q0, O1, Q2. and O3 reset clears the outputs of the counter to 0. En enables the counting when En-1. When En-0, the counter stops. The counter sequentially counts all the possible numbers and loops again, from 0 to 9, back to 0 and 9, etc Design C-2: Ten-second Counter with LED display. Generate 1 Hz clock signal (please follow Lab 2 Part II). Use your four-bit up-counter in Design C-1 as a component to construct a modulo-10 counter. Then, connect the 1 Hz clock as the clock input of the modulo-10 up-counter. Also, connect a BCD-to-seven segment display converter (please use Lab 8, Design A) with the counter to display the counting numbers Seconds One's digit q0 ql Modulo-10 q3 counter BCD-to f 7-seg- 9 converter CLK reset RESET Figure 3. Ten-second counter

Answer 1

program:
design 1:
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity mod10_counter is
   port(
      clk, reset: in std_logic;
      q: out std_logic_vector(3 downto 0)
   );
end mod10_counter;

architecture two_seg_arch of mod10_counter is
   constant TEN: integer := 10;
   signal r_reg: unsigned(3 downto 0);
   signal r_next: unsigned(3 downto 0);
begin
   -- register
   process(clk,reset)
   begin
      if (reset='1') then
         r_reg <= (others=>'0');
      elsif (clk'event and clk='1') then
         r_reg <= r_next;
      end if;
   end process;
   -- next-state logic
   r_next <= (others=>'0') when r_reg=(TEN-1) else
             r_reg + 1;
   -- output logic
   q <= std_logic_vector(r_reg);
end two_seg_arch;

Design2:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity test is
port (
clk : in std_logic;
bcd : in std_logic_vector(3 downto 0);  --BCD input
segment7 : out std_logic_vector(6 downto 0) -- 7 bit decoded output.
  );
end test;
--'a' corresponds to MSB of segment7 and g corresponds to LSB of segment7.
architecture Behavioral of test is

begin
process (clk,bcd)
BEGIN
if (clk'event and clk='1') then
case  bcd is
when "0000"=> segment7 <="0000001";  -- '0'
when "0001"=> segment7 <="1001111";  -- '1'
when "0010"=> segment7 <="0010010";  -- '2'
when "0011"=> segment7 <="0000110";  -- '3'
when "0100"=> segment7 <="1001100";  -- '4'
when "0101"=> segment7 <="0100100";  -- '5'
when "0110"=> segment7 <="0100000";  -- '6'
when "0111"=> segment7 <="0001111";  -- '7'
when "1000"=> segment7 <="0000000";  -- '8'
when "1001"=> segment7 <="0000100";  -- '9'
--nothing is displayed when a number more than 9 is given as input.
when others=> segment7 <="1111111";
end case;
end if;

end process;

end Behavioral;