Question

ww DECADE achive vhdk design exty Clock D> /clock ResePeset chel asvn COUNTER o2 INI Op 1' → Count up > count down gates the rect nunber for fium Oto and 'E' for ofther b'harj b LED ghtue when ceunt down to Yoood or count number IAN 3 Reset no J DISPLAY DRIVER and becade Counter 曰 MENU

This is a subject on "Design of logic systems", using VHDL codes. Thank you.

Also, note that the limitations that I cannot use vector in the input and output variables. Thank you

Answer 1

-- Notes:

--1)This counter will count upto 9 and then it becomes zero.then count again. simillarly down counter.

--2)In Logic Gates LED will be always '1' why becuase counter will be 0 to 9 always. in case of changes we have to do changes first in bcd counter.

--3)There are 3 testbenches if you can check clearly. Those are testbenches for decade_counter, counter alone and bcd_to_seven_segment entities as asked in the question for simulations.

--4)For any modifications if needed comment below. feel free to ask.

-- BCD up/down counter 0 upto 9
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.std_logic_unsigned.all;

entity counter is
Port ( Clock,Reset,Ctrl : in STD_LOGIC;
O0,O1,O2,O3 : out STD_LOGIC);
end counter;

architecture Behavioral of counter is

signal count : STD_LOGIC_VECTOR (3 downto 0);
begin
process(Clock,Reset)
begin
if(Reset='1') then
count <= (others=> '0');
elsif(rising_edge(Clock)) then
if(Ctrl='1') then
   -- if you want to run counter from 0 to 15 remove if block inside this if block
   -- Add this : count <= count + 1;
if(count = 9) then
count <= "0000";
       -- if you want to stop counter after 9 you can use line below here
       -- count <= count;
else
count <= count + 1;
end if;
   else
   -- if you want to run counter from 15 to 0 remove if block inside this else block
   -- Add this : count <= count - 1;
   if(count = 0) then
count <= "1001";
       -- if you want to stop counter after 0 you can use line below here
       -- count <= count;
else
count <= count - 1;
end if;
end if;
end if;
end process;
O0 <= count(0);
O1 <= count(1);
O2 <= count(2);
O3 <= count(3);

end Behavioral;

--7 segment block vhdl code
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity bcd_2_7seg is
Port ( IN0,IN1,IN2,IN3: in STD_LOGIC;
a,b,c,d,e,f,g : out STD_LOGIC);
end bcd_2_7seg;

architecture Behavioral of bcd_2_7seg is
signal bcd_in : STD_LOGIC_VECTOR (3 downto 0);
signal seg_out : STD_LOGIC_VECTOR (6 downto 0);
begin

bcd_in <= IN3 & IN2 & IN1 & IN0;
-- Using case statement
process(bcd_in)
begin
case (bcd_in) is
when "0000" =>
seg_out <= "0000001"; ---0
when "0001" =>
seg_out <= "1001111"; ---1
when "0010" =>
seg_out <= "0010010"; ---2
when "0011" =>
seg_out <= "0000110"; ---3
when "0100" =>
seg_out <= "1001100"; ---4
when "0101" =>
seg_out <= "0100100"; ---5
when "0110" =>
seg_out <= "0100000"; ---6
when "0111" =>
seg_out <= "0001111"; ---7
when "1000" =>
seg_out <= "0000000"; ---8
when "1001" =>
seg_out <= "0000100"; ---9
when others =>
seg_out <= "0110000"; ---E
end case;

end process;
a <= seg_out(6);
b <= seg_out(5);
c <= seg_out(4);
d <= seg_out(3);
e <= seg_out(2);
f <= seg_out(1);
g <= seg_out(0);

end Behavioral;

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.std_logic_unsigned.all;

entity logic_gates is
Port ( Ctrl,IN0,IN1,IN2,IN3 : in STD_LOGIC;
LED : out STD_LOGIC);
end logic_gates;

architecture Behavioral of logic_gates is
signal count : STD_LOGIC_VECTOR(3 downto 0);

begin
count <= IN3 & IN2 & IN1 & IN0;
process (count,ctrl)
begin
-- if(Ctrl = '1')
if(Ctrl = '1' or Ctrl = '0') then --Acutally there is no need of Ctrl signal
if(count <= 9) then -- You are giving to bcd counter which you will not get this else part(count: 10-15).
   LED <= '1';
else
   LED <= '0';
       end if;
--   else
--   if( count >= 9 and count = 0) then
--       LED <= '1';
--       else
--       LED <= '0';
--       end if;
   end if;
end process;
  
end Behavioral;

-- Decade counter vhdl code.
-- This is top component. inside it components like counter,7 segment and logic_gates block used
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity decade_counter is
Port ( Clock,Reset,Ctrl : in STD_LOGIC;
a,b,c,d,e,f,g,LED : out STD_LOGIC);
end decade_counter;

architecture Behavioral of decade_counter is
component counter
Port ( Clock,Reset,Ctrl : in STD_LOGIC;
O0,O1,O2,O3 : out STD_LOGIC);
end component;

component bcd_2_7seg
Port ( IN0,IN1,IN2,IN3: in STD_LOGIC;
a,b,c,d,e,f,g : out STD_LOGIC);
end component;
component logic_gates
Port ( Ctrl,IN0,IN1,IN2,IN3 : in STD_LOGIC;
LED : out STD_LOGIC);
end component;

signal IN0,IN1,IN2,IN3 : STD_LOGIC;
begin
counter_inst: counter port map(Clock => Clock,
Reset => Reset,
                                           Ctrl => Ctrl,
                                           O0 => IN0,
                                           O1 => IN1,
                                           O2 => IN2,
                                           O3 => IN3
                                           );
bcd_2_7seg_inst: bcd_2_7seg Port map( IN0 => IN0,
IN1 => IN1,
IN2 => IN2,
IN3 => IN3,
                                                   a => a,
                                                   b => b,
                                                   c => c,
                                                   d => d,
                                                   e => e,
                                                   f => f,
                                                   g => g
                                                   );
logic_gates_inst: logic_gates port map(Ctrl => Ctrl,
                                           IN0 => IN0,
IN1 => IN1,
IN2 => IN2,
IN3 => IN3,
                                                   LED => LED
                                           );
                                                     
end Behavioral;

--Testbench for Decade Counter
library IEEE;
use IEEE.Std_logic_1164.all;
use IEEE.Numeric_Std.all;

entity decade_counter_tb is
end;

architecture testbench of decade_counter_tb is

component decade_counter
Port ( Clock,Reset,Ctrl : in STD_LOGIC;
a,b,c,d,e,f,g,LED : out STD_LOGIC);
end component;

signal Clock,Reset,Ctrl: STD_LOGIC;
signal a,b,c,d,e,f,g,LED: STD_LOGIC;

constant clock_period: time := 10 ns;
signal stop_the_clock: boolean;
begin

uut: decade_counter port map ( Clock => Clock,
Reset => Reset,
Ctrl => Ctrl,
a => a,
b => b,
c => c,
d => d,
e => e,
f => f,
g => g,
LED => LED );
Reseting: process
begin
Reset <= '1';
   wait for 2500 ps;
   Reset <= '0';
wait;
end process;
stimulus: process
begin
   Ctrl <= '1';
   wait for 30 ns;
   Ctrl <= '0';
   wait for 110 ns;
   Ctrl <= '1';
   wait for 120 ns;
     
stop_the_clock <= true;
wait;
end process;

clocking: process
begin
while not stop_the_clock loop
Clock <= '0', '1' after clock_period / 2;
wait for clock_period;
end loop;
wait;
end process;
end;

--Simulation waveform for Decade counter

ISE-14.7 VIRTUALAPPLIANCE IRunning - Oracle VM VirtualBox Applications Places System Sat Apr 20, 1:13 PM Float (P.20160913) [Default.wcfg1 200 6 Default wcfg Sim Time: 270,000 ps G terminal ISE Project Navigator ..ISim (P20160913) Float (P20160913)-

-- Testbench for Counter - BCD 0 to 9 and 9 to 0
library IEEE;
use IEEE.Std_logic_1164.all;
use IEEE.Numeric_Std.all;

entity counter_tb is
end;

architecture testbench of counter_tb is

component counter
Port ( Clock,Reset,Ctrl : in STD_LOGIC;
O0,O1,O2,O3 : out STD_LOGIC);
end component;

signal Clock,Reset,Ctrl: STD_LOGIC;
signal O0,O1,O2,O3: STD_LOGIC;

constant clock_period: time := 10 ns;
signal stop_the_clock: boolean;

begin

uut: counter port map ( Clock => Clock,
Reset => Reset,
Ctrl => Ctrl,
O0 => O0,
O1 => O1,
O2 => O2,
O3 => O3 );

Reseting: process
begin
Reset <= '1';
   wait for 2500 ps;
   Reset <= '0';
wait;
end process;
stimulus: process
begin
   Ctrl <= '1';
   wait for 30 ns;
   Ctrl <= '0';
   wait for 110 ns;
   Ctrl <= '1';
   wait for 120 ns;
     
stop_the_clock <= true;
wait;
end process;
  
clocking: process
begin
while not stop_the_clock loop
Clock <= '0', '1' after clock_period / 2;
wait for clock_period;
end loop;
wait;
end process;

end;
  

-- Simulation waveform for Counter - BCD

ISE-14.7 VIRTUALAPPLIANCE IRunning - Oracle VM VirtualBox Applications Places System Sat Apr 20, 1:17 PM Float (P.20160913) [Default.wcfg1 200 6 Default wcfg Sim Time: 270,000 ps FlaatLP.201609131T İkisim(R20160913) Terminall ISE Project Navigator ISim (P.20160913 Flcat (P20160913-

-- Testbench for BCD to 7 segment display vhdl code
library IEEE;
use IEEE.Std_logic_1164.all;
use IEEE.Numeric_Std.all;

entity bcd_2_7seg_tb is
end;

architecture testbench of bcd_2_7seg_tb is

component bcd_2_7seg
Port ( IN0,IN1,IN2,IN3: in STD_LOGIC;
a,b,c,d,e,f,g : out STD_LOGIC);
end component;

signal IN0,IN1,IN2,IN3: STD_LOGIC;
signal a,b,c,d,e,f,g: STD_LOGIC;

begin

uut: bcd_2_7seg port map ( IN0 => IN0,
IN1 => IN1,
IN2 => IN2,
IN3 => IN3,
a => a,
b => b,
c => c,
d => d,
e => e,
f => f,
g => g );

stimulus: process
begin
IN3 <= '0';IN2 <= '0';IN1 <= '0';IN0 <= '0'; wait for 10 ns;
IN3 <= '0';IN2 <= '0';IN1 <= '0';IN0 <= '1'; wait for 10 ns;
IN3 <= '0';IN2 <= '0';IN1 <= '1';IN0 <= '0'; wait for 10 ns;
IN3 <= '0';IN2 <= '0';IN1 <= '1';IN0 <= '1'; wait for 10 ns;
IN3 <= '0';IN2 <= '1';IN1 <= '0';IN0 <= '0'; wait for 10 ns;
IN3 <= '0';IN2 <= '1';IN1 <= '0';IN0 <= '1'; wait for 10 ns;
IN3 <= '0';IN2 <= '1';IN1 <= '1';IN0 <= '0'; wait for 10 ns;
IN3 <= '0';IN2 <= '1';IN1 <= '1';IN0 <= '1'; wait for 10 ns;
IN3 <= '1';IN2 <= '0';IN1 <= '0';IN0 <= '0'; wait for 10 ns;
IN3 <= '1';IN2 <= '0';IN1 <= '0';IN0 <= '1'; wait for 10 ns;
IN3 <= '1';IN2 <= '0';IN1 <= '1';IN0 <= '0'; wait for 10 ns;
IN3 <= '1';IN2 <= '0';IN1 <= '1';IN0 <= '1'; wait for 10 ns;
IN3 <= '1';IN2 <= '1';IN1 <= '0';IN0 <= '0'; wait for 10 ns;
IN3 <= '1';IN2 <= '1';IN1 <= '0';IN0 <= '1'; wait for 10 ns;
IN3 <= '1';IN2 <= '1';IN1 <= '1';IN0 <= '0'; wait for 10 ns;
IN3 <= '1';IN2 <= '1';IN1 <= '1';IN0 <= '1'; wait for 10 ns;
wait;
end process;

end;

--Simulation waveform for bcd_2_7seg

ISE-14.7 VIRTUALAPPLIANCE IRunning - Oracle VM VirtualBox 焦Applications Places System Sat Apr 20, 1:25 PM Float (P20160913) [Default.wcfgl Default.wcfg Sim Time: 160,000 ps ISE Project Navigator ...ISim (P20160913)ISim (P20160913) Float (P20160913)-. Terminall