Question

Design in VHDL a 4-bit up-down counter as presented below:

XЗ Q3 X3X2X1X0 Parallel Load X2 S1SO Function Select Input Q2 RST-Asynchronous Reset Input X1 CLK- Clock Input Q1 хо Q3Q2Q1Q0 - Parallel Output Q0 CLK S1 S0 RST

The operation of the up-down counter is described by the following truth table:

S1 S0	Action
0 0	Hold
0 1	Count up
1 0	Count down
1 1	Parallel Load

Provide VHDL code and testbench

Answer 1

--VHDL Code

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity up_down_counter is
   port (   X3, X2, X1, X0   : in std_logic;
       CLK       : in std_logic;
       S1, S0       : in std_logic;
       RST       : in std_logic;
       Q3, Q2, Q1, Q0   : out std_logic
   );
end up_down_counter;

architecture arch of up_down_counter is

signal reg :std_logic_vector(3 downto 0):= "0000";

signal sel :std_logic_vector(1 downto 0);

begin

sel <= (S1 & S0);

process (CLK, RST)

begin

   if (RST = '1') then --Asynchronous reset
       reg <= "0000";
   else

       if rising_edge (CLK) then
       case (sel) is
           when "00"=> reg <= reg;
           when "01"=> reg <= reg + 1;
           when "10"=> reg <= reg - 1;
           when "11"=> reg <= (X3 & X2 & X1 & X0);
           when others => null;
       end case;
       end if;
   end if;

end process;

Q3 <= reg(3);
Q2 <= reg(2);
Q1 <= reg(1);
Q0 <= reg(0);

end arch;

----------------------------------------------------------------------------------------------------------------------------------------------------------------

--VHDL TESTBENCH

library IEEE;
use IEEE.Std_logic_1164.all;
use IEEE.Numeric_Std.all;

entity up_down_counter_tb is
end;

architecture bench of up_down_counter_tb is

component up_down_counter
   port (   X3, X2, X1, X0   : in std_logic;
       CLK       : in std_logic;
       S1, S0       : in std_logic;
       RST       : in std_logic;
       Q3, Q2, Q1, Q0   : out std_logic
   );
end component;

signal X3, X2, X1, X0: std_logic;
signal CLK: std_logic;
signal S1, S0: std_logic;
signal RST: std_logic;
signal Q3, Q2, Q1, Q0: std_logic ;

begin

uut: up_down_counter port map ( X3 => X3,
X2 => X2,
X1 => X1,
X0 => X0,
CLK => CLK,
S1 => S1,
S0 => S0,
RST => RST,
Q3 => Q3,
Q2 => Q2,
Q1 => Q1,
Q0 => Q0 );

CLOCK: process
begin
  
   CLK <= '0';
   wait for 10 ns;
   CLK <= '1';
   wait for 10 ns;
end process;

STIMULUS: process
begin
  
   X3 <= '1';
   X2 <= '0';
   X1 <= '0';
   X0 <= '0';
   RST <= '0';
   S1 <= '0';
   S0 <= '0';

   wait for 100 ns;

   S1 <= '0';
   S0 <= '1';

   wait for 100 ns;

   RST <= '1';

   wait for 100 ns;

   RST <= '0';
   S1 <= '1';
   S0 <= '0';

   wait for 100 ns;

   S1 <= '1';
   S0 <= '1';

wait;
end process;

end;

----------------------------------------------------------------------------------------------------------------------------------------------------

--Simulation on ModelSim

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