Question

Lab 7:

Design a 4 bit register in VHDL. The register file has a synchronous load signal and an asynchronous reset. When the reset signal is high the register file should be cleared. The input is stored only when the load and clock signal is high. 

Answer 1

-- VHDL code for 4 bit register

--library declaration

library IEEE;

use IEEE.std_logic_1164.all;

--entity declaration for 4 bit register

entity register_4bit is

port(

clk : in std_logic; -- clock input

reset: in std_logic ; -- Asynchronous reset input

load: in std_logic ; --synchronous load input

D: in std_logic_vector(3 downto 0); --4 bit data input to register

Q: out std_logic_vector(3 downto 0) -- 4 bit register output

);

end register_4bit;

--architecture body declaration for 4 bit register

architecture behavioral of register_4bit is

begin

process (clk,reset)

begin

--when reset is high, register is cleared

if(reset = '1') then

Q <= "0000";

--if not reset and load is high during postive edge occurance of clock , then data D is loaded into register

elsif (CLK'event and CLK='1') then

if (load = '1') then

Q <= D;

end if;

end if;

end process;

end behavioral;

-- VHDL Testbench code for 4 bit register

library IEEE;

use IEEE.std_logic_1164.all;

--entity declaration for testbench

entity test_reg is

end test_reg;

--architecture declaration for testbench

architecture behavioral of test_reg is

--component instantiation of 4 bit register

component register_4bit is

port(

clk : in std_logic; -- clock input

reset: in std_logic ; -- Asynchronous reset input

load: in std_logic ; --synchronous load input

D: in std_logic_vector(3 downto 0); --4 bit data input to register

Q: out std_logic_vector(3 downto 0) -- 4 bit register output

);

end component ;

--internal signal declarations

signal clk: std_logic;

signal reset: std_logic;

signal load: std_logic;

signal D: std_logic_vector(3 downto 0);

signal Q: std_logic_vector(3 downto 0);

  

begin

  

--port mapping of 4 bit register

DUT: register_4bit port map ( clk => clk,

reset => reset,

load => load,

D => D,

Q => Q );

--clock input generation

clock_proc:process

begin

clk <= '0';

wait for 5 ns;

clk <= '1';

wait for 5 ns;

end process;

--input generation

stim_proc:process

begin

reset <= '1'; load <= '0'; D <= "0000";

wait for 10 ns;

reset <= '0'; load <= '0'; D <= "0010";

wait for 10 ns;

reset <= '0'; load <= '1'; D <= "0110";

wait for 10 ns;

reset <= '0'; load <= '1'; D <= "0010";

wait for 10 ns;

reset <= '0'; load <= '0'; D <= "0100";

wait for 10 ns;

reset <= '1'; load <= '1'; D <= "0010";

wait for 10 ns;

reset <= '0'; load <= '0'; D <= "1111";

wait for 10 ns;

reset <= '0'; load <= '1'; D <= "0100";

wait for 10 ns;

reset <= '1'; load <= '0'; D <= "0010";

wait for 10 ns;

reset <= '0'; load <= '1'; D <= "1111";

wait for 10 ns;

reset <= '0'; load <= '0'; D <= "0010";

wait ;

end process;

end behavioral;

-- simulation waveforms