Question

1 Simulations to verify a 4-bit Register Simulate and verify a 4-bit Register using behavioral VHDL code in ModelSim. Recall

ENABLE Register 0000 (a) Schematic of a 4-bit Register (b) Schematic of a 4-bit Register DO ENABLE QUE Q . 0000 0001 0001 001

0 0
Add a comment Improve this question Transcribed image text
Answer #1

entity register is

port (clk, en: in std_logic;

D: in std_logic_vector(3 down to 0)

Q: out std_logic_vector(3 down to 0));

end register

architecture behavioral of register is

begin

process(D,clk)

begin

if(en='0')

Q<=0000;

endif

else

Q<= D;

endprocess;

end behavioral

In the above program

D is input of 4 bit and Q is output Here we used En has 'enable' pin if enable is 0 then Q will be assigned as 0000 else q will be assigned by D

Add a comment
Know the answer?
Add Answer to:
1 Simulations to verify a 4-bit Register Simulate and verify a 4-bit Register using behavioral VHDL...
Your Answer:

Post as a guest

Your Name:

What's your source?

Earn Coins

Coins can be redeemed for fabulous gifts.

Not the answer you're looking for? Ask your own homework help question. Our experts will answer your question WITHIN MINUTES for Free.
Similar Homework Help Questions
  • Base no bit 0 0 Q-2 (25p): Assume that logical addresses are 16-bit long: 3 bits...

    Base no bit 0 0 Q-2 (25p): Assume that logical addresses are 16-bit long: 3 bits for segment no and 13 bits for offset. Segment table of the currently running process is given below: a) (5) How many segments can this Segment Present Modify Length process have at maximum? bit 0 00100 0111 0000 0100 0000 1000 0100 b) (15) Convert the following logical 10100 0100 0001 0010 0010 1100 1000 address to physical (real) address. 2 01100 0100 0000...

  • Objective: In this lab, we will learn how we can design sequential circuits using behavioral mode...

    Just need the code for the random counter,Thanks Objective: In this lab, we will learn how we can design sequential circuits using behavioral modelling, and implementing the design in FPGA. Problem: Design a random counter with the following counting sequence: Counting Sequence: 04 2 9 168573 Design Description: The counter has one clock (Clock), one reset (Reset), and one move left or right control signal (L/R) as input. The counter also has one 4bit output O and one 2bit output...

  • DO bit 0 1 Q-2 (25p): Assume that logical addresses are 16-bit long: 3 bits for...

    DO bit 0 1 Q-2 (25p): Assume that logical addresses are 16-bit long: 3 bits for segment no and 13 bits for offset. Segment table of the currently running process is given below: a) (5) How many segments can this Segment Present Modify process have at maximum? Length bit Base 0 0 0 0100 0111 0000 0100 0000 1000 0100 b) (15) Convert the following logical 1 1 0100 0100 0001 0010 0010 1100 1000 address to physical (real) address...

  • 3. (2 10 20 points) Design a decade counter using a 2-4-2-1 weighted code for decimal...

    3. (2 10 20 points) Design a decade counter using a 2-4-2-1 weighted code for decimal digits (see table below) using the following flip-flop types: a. D Flip-flops S-R Flip-flops b. Digit ABCD 0000 1 0001 2 0010 3 0011 4 0100 1011 6 1100 7 1101 8 1110 1111 4. (6 points) Redraw the circuit from problem 3.a. using NAND gates only. 3. (2 10 20 points) Design a decade counter using a 2-4-2-1 weighted code for decimal digits...

  • Question 1.1. (TCO 1) Which number system has a radix of two? (Points : 4) Hexadecimal...

    Question 1.1. (TCO 1) Which number system has a radix of two? (Points : 4) Hexadecimal Binary Decimal Octal Question 2.2. (TCO 1) Convert 24 base 10 to hexadecimal. (Points : 4) 1A 18 20 30 Question 3.3. (TCO 1) If FF h is converted to decimal, the result is _____. (Points : 4) 100 200 255 256 Question 4.4. (TCO 1) Convert decimal 103 to an 8-bit binary number. (Points : 4) 1110 0100 0100 0000 0110 0111 0110...

  • We have learned a famous shift cipher called Caesar Cipher. Now if we are given a...

    We have learned a famous shift cipher called Caesar Cipher. Now if we are given a plain test: THE ART OF WARAnd key = 3 (a shift by 3 letters), please give the ciphertext Given an 8 bit block P = 10101111 and a key K = 01101011, please give the result of bitwise XOR between P and K Please give the left 2 shift of the 8 bit text 01100101 Use the given a permutation table 23614857 to define...

  • Arduino. DEC HEX BIN(4-bits) Introducing ARDUINO 0 0 0000 1 1 0001 2 2 0010 3...

    Arduino. DEC HEX BIN(4-bits) Introducing ARDUINO 0 0 0000 1 1 0001 2 2 0010 3 3 0011 4 4 0100 5 5 0101 How many 1/0 of Port-D? How many usable 1/0 of Port-D, if Serial-Communication is in-used? What is the Arduino's pin assignment of ATMEL's PC5, PB3, & PD1*? What is the ATMEL's pin assignment of Arduino's D13*, D1, & D19? To complete the table about Number System Conversion (shown your step) 6 6 0110 7 7 0111...

  • A 4-bit register is initially at 1011. The register is parallel-loaded with 1010, and then right-shifted...

    A 4-bit register is initially at 1011. The register is parallel-loaded with 1010, and then right-shifted with Din 1. The final state of the register is (a) 0011 (b) 0100 (c) 0101 (d) 1010 (e) 1101 9.

  • Implement the following bit sequential Adder-Subtractor design. X and Y are two operand inputs and Z...

    Implement the following bit sequential Adder-Subtractor design. X and Y are two operand inputs and Z is for the control signal i.e. Z is the selection bit. When Z has value 0, the circuit is an adder, meanwhile, the D flip-flop should be initialized to 0 for each addition. When Z has value 1, it performs subtraction, meanwhile, the D flip-flop should be initialized to 1 for each subtraction. Test your Adder-Subtractor circuit on the following operations and use the...

  • Please explain why 1010???? and also why c can be represent in that way? please draw table error...

    please explain why 1010???? and also why c can be represent in that way? please draw table error code 9:07 No SIM For an integer n greater than or equal to 0, a code g that associates it with a 4-bit code word g (n) is obtained as shown on the right, but it is assumed that the following condition is satisfied 10001 2 0011 3 0010 0110 5 0111 6 0101 7 0100 8 1100, 9 1101 . For...

ADVERTISEMENT
Free Homework Help App
Download From Google Play
Scan Your Homework
to Get Instant Free Answers
Need Online Homework Help?
Ask a Question
Get Answers For Free
Most questions answered within 3 hours.
ADVERTISEMENT
ADVERTISEMENT
Active Questions
ADVERTISEMENT