Question

Just need the code for the random counter,Thanks

Objective: In this lab, we will learn how we can design sequential circuits using behavioral modelling, and implementing the design in FPGA. Problem: Design a random counter with the following counting sequence: Counting Sequence: 04 2 9 168573 Design Description: The counter has one clock (Clock), one reset (Reset), and one move left or right control signal (L/R) as input. The counter also has one 4bit output O and one 2bit output S. The output S is used to select the HEX display for the number represented by O The operation is listed below with some example current output and expected output: Seq.ClockResetL/R Current Output Expected Output | 0100 0010 1001 0001 0110 1000 0101 0111 0011 10 0100 0010 1001 0001 0110 1000 0101 0111 0011 01 10 01 10 0100 0010 1001 0001 0110 1000 0101 0111 0011 12 0100 0010 1001 0001 0110 1000 0101 0111 0011 16 18 20 "means a positive clock edge, "X" means don't care and "means any value So, whenever Reset is 0, the output will be "0000". For the push buttons in the DEl board, when they are not pressed the value is 1, and when pressed the value is 0 When Reset is 1, L/R is 1, and there is a positive clock edge: The counter updates its output value with the next number in the counting sequence. Also, if the current value is displayed in HEX n the updated value is displayed in HEX n+1, where n- (0,1,23. If the current value is displayed in HEX3, then the updated value is displayed in HEX0. This selection of the display is determined using the S output of the counter. When Reset is 1, L/R is 0, and there is a positive clock edge: The counter updates its output value with the next number in the counting sequence. Also, if the current value is displayed in HEX n, the updated value is displayed in HEX n-1, where n-(3,2,13. If the current value is displayed in HEXO, then the updated value is displayed in HEX3. This selection of the display is determined using the S output of the counter. Procedure: 1. Create a new folder named "lab 8". 2. Create a new project inside this folder. The name of your project will be "Random Counter". 3. Copy the provided verilog file "Random Counter.v" inside this folder (i.e. lab 8) and add this file to your project. Set this as the top-level entity. 4. Write a module Counter in the Random Counter.v that implements the functionality described in the problem statement. 5. Copy the Verilog file for the BCD to seven segment decoder from lab 6 and update the code. (Add an enable input to your decoder such that the decoder only converts the input data to seven segment code only if the enable input is 1, else the output should be 7'b1111111.) 6. Write a module for 2 to 4 binary decoder (2 bit input and 4 bit output). As this is a binary decoder, only one output will be 1 at any point in time based on the input. No enable is required for this decoder. 7. In the Random Counter module a. Declare an instance of the Counter module. For the inputs to this Counter module, connect KEY[0], KEY[1] with the clock and Reset, SW[O] with the L/R input. The 4bit output from the counter is connected to the data inputs of all the BCD to seven segment decoders using wires. The S output from the counter is connected to the input of a 2 to 4 decoder using wires b. Instantiate a 2 to 4 decoder in the Random Counter module. Each output of the decoder is connected to the enable input of a BCD to seven segment display decoder c. Instantiate the BCD to seven segment decoders in the Random Counter module. d. The output of the BCD to seven segment decoders are connected to the HEX0, HEX1 HEX2 and HEX3 output pins declared in the Random _Counter module. A block diagram of your circuit is provided below 7. Compile your code and program the FPGA (Instructions provided in lab 6) 2 to 4 binaryEnable decoder Decoder HEX 0 Display in the DE1 board BCD to seven segment decoder 0 HEX 0 KEY[0] KEYI11 Clock 2bit S Reset 4bit Counter SW[0] L/R BCD to HEX 3 Display in the DE1 board HEX 3 seven segment decoder 3 Random Counter Figure: Block diagram of the random counter Report: Your report should contain 1. A title page should atleast contain your and your partners name, tech ids, lab number and a title "Design of random counter" 2. State the problem 3. Draw a block diagram for your design 4. Description of how your design will work. 5. Code for your module.

Answer 1

// Counter Block in Whole Micro-Architechture of Random_Counter
module counter(
//Input Ports
input Clock,
input Reset,
input L,
//Output Ports
output reg [3:0] O,
output reg [1:0] S
);
//Internal Wires and Regs
reg [1:0]S_w;
reg [3:0]O_w;

//Sequential Block
always@(posedge Clock or negedge Reset) begin
if(~Reset) begin // Asynchronous active low reset
O <= 4'b0000;
   S <= 2'b00;
end
else begin
O <= O_w;
S <= S_w;
end
end

//Combinational Block for O output
always@(O or L) begin // When input or counter transition this block trigger
case(O)
4'b0000 : O_w = 4'b0100;
4'b0100 : O_w = 4'b0010;
4'b0010 : O_w = 4'b1001;
4'b1001 : O_w = 4'b0001;
4'b0001 : O_w = 4'b0110;
4'b0110 : O_w = 4'b1000;
4'b1000 : O_w = 4'b0101;
   4'b0101 : O_w = 4'b0111;  
   4'b0111 : O_w = 4'b0011;  
   4'b0011 : O_w = 4'b0000;
   default : O_w = 4'b0000; //Default is given to remove latches when using mux.
endcase
end
  
//Combinational Block for S output
always@(O or L) begin
if(L) begin
   case(O)
4'b0000 : S_w = 2'b01;
4'b0100 : S_w = 2'b10;
4'b0010 : S_w = 2'b11;
4'b1001 : S_w = 2'b00;
4'b0001 : S_w = 2'b01;
4'b0110 : S_w = 2'b10;
4'b1000 : S_w = 2'b11;
4'b0101 : S_w = 2'b00;  
   4'b0111 : S_w = 2'b01;  
   4'b0011 : S_w = 2'b10;
   default : S_w = 2'b00; //Default is given to remove latches when using mux.
endcase
end
else begin
   case(O)
4'b0000 : S_w = 2'b01;
4'b0100 : S_w = 2'b00;
4'b0010 : S_w = 2'b11;
4'b1001 : S_w = 2'b10;
4'b0001 : S_w = 2'b01;
4'b0110 : S_w = 2'b00;
4'b1000 : S_w = 2'b11;
4'b0101 : S_w = 2'b10;  
   4'b0111 : S_w = 2'b01;  
   4'b0011 : S_w = 2'b00;
   default : S_w = 2'b00; //Default is given to remove latches when using mux.
endcase
end
end
endmodule
  
//Binary Decoder 2 to 4 Verilog code module
module binary_decoder_2_4(
//Input Port
input [1:0]S,
//Output Ports
output reg Y0,Y1,Y2,Y3
);

//Binary Decoder Logic
always@(*) begin
case(S)
2'b00 : {Y0,Y1,Y2,Y3} = 4'b1000;
2'b01 : {Y0,Y1,Y2,Y3} = 4'b0100;
2'b10 : {Y0,Y1,Y2,Y3} = 4'b0010;
2'b11 : {Y0,Y1,Y2,Y3} = 4'b0001;
endcase
end
  
endmodule

//BCD to 7 Segment Decoder common cathode
module bcd_7_seg(
//Input Ports
input enable, //Decoder enable or disable
input [3:0]bcd,
//Output Port
output reg [6:0]HEX_O
);

//Combinational Block for BCD to 7 Segment Decoder Common cathode
//For common anode we have to invert 1's to 0's and 0's to 1's
always @(*) begin
if(enable) begin
case(bcd)
4'b0000: HEX_O = 7'b0000001; // "0"
4'b0001: HEX_O = 7'b1001111; // "1"
4'b0010: HEX_O = 7'b0010010; // "2"
4'b0011: HEX_O = 7'b0000110; // "3"
4'b0100: HEX_O = 7'b1001100; // "4"
4'b0101: HEX_O = 7'b0100100; // "5"
4'b0110: HEX_O = 7'b0100000; // "6"
4'b0111: HEX_O = 7'b0001111; // "7"
4'b1000: HEX_O = 7'b0000000; // "8"
4'b1001: HEX_O = 7'b0000100; // "9"
default: HEX_O = 7'b0000001; // "0"
endcase
end
else begin
HEX_O = 7'b1111111; //If enable is "0"
end
end

endmodule

//Random_Counter Verilog Code Top module

module Random_Counter(
//Input Ports
input [1:0]KEY,
input SW,
//Output Ports
output [6:0]HEX0,HEX1,HEX2,HEX3
);
//Declaration of Internal Wires required to connect between modules instances
wire [1:0]S;
wire [3:0]O;
wire Y0,Y1,Y2,Y3;

//Modules Instantiation for counter,binary decoder, 7 segment decoder
counter COUNTER_INST(KEY[0],KEY[1],SW,O,S);
binary_decoder_2_4 BINARY_DECODER_INST(S,Y0,Y1,Y2,Y3);
bcd_7_seg BCD_TO_7_SEG_INST_0(Y0,O,HEX0);
bcd_7_seg BCD_TO_7_SEG_INST_1(Y1,O,HEX1);
bcd_7_seg BCD_TO_7_SEG_INST_2(Y2,O,HEX2);
bcd_7_seg BCD_TO_7_SEG_INST_3(Y3,O,HEX3);

endmodule

//Testbench for Random Counter
//DUT means Random Counter here
module test;
reg Clock,Reset,SW; //Regs to Drive stimulus to DUT inputs
wire [6:0]HEX0,HEX1,HEX2,HEX3; //Wires to connect for DUT outputs

//Clock Generation
always begin
#5 Clock = 1'b1;
#5 Clock = 1'b0;
end

//Instantiation of DUT - Random_Counter
Random_Counter RANDOM_COUNTER_INST(
.KEY({Reset,Clock}),
.SW(SW),
.HEX0(HEX0),
.HEX1(HEX1),
.HEX2(HEX2),
.HEX3(HEX3)
);
  
//Driving Stimulus to DUT(Random_Counter)
initial begin
SW = 1'b0;
Reset = 1'b0; // Asynchronous active low reset
#15 Reset = 1'b1;
SW = 1'b1;
#100 SW = 1'b0;
#100 $finish; // Finishing the simulation
end
endmodule

//Simulation Waveform

1)

Wave - Default test,RANDOM COUNTER INST /SW 1h1 /test,RANDOM COLUNTER INST HEX2 7h12 Y3 1h 215 rs Cursor

2)

Wave - Default test,RANDOM COUNTER INST /SW 1h1 test,RANDOM COUNTER INST HEX2 7h12 215ns aursor 1