Question

please answer question 4 (all parts of question4 please) will rate!

3. (30 pts) Design a 2-bit Gray code generator that ropetitively delivers the sequence 00301911-10-00when the input signal UP- 1,or in reverse order 009 10기け01 →00→ when UP-0. Your design should include an asynchronous low. active reset operation: the FSM goes to 00 state when a reset signal is applied In addition to the state output z[1). 2[0]. there is a carry/borrow output bit e which is I when state-11 and up-1 or when state-00 and up-0. up gray code「 - clock| counter- z reset 1) Complete the state transition diagram. 2) Write the Verilog program. module gray2(clock, reset, up, z, c); ndmodule 4. (20 pts) If you are asked to implement your design of prob. 3 on DE2 board by following the instructions below a) Use the 50 MHz clock CLOCK 50 from the board; b) Use KEYO as reset control c) Use SWO as UP (down) control. d) Use HEXO to display the decimal value 0-3 of the gray code with refresh rate of I㎐ e) Use LEDG0 to as indicator for the carry bit Assuming that the modules as available are readily available. freq div(clock_in, scale, clock out);/ clock out frequeny //clock in frequency/2 scale bed2seg7(bed, hex);4-bit bed to low active 7 segment display gray2(clock, reset, up, z, c);I 2-bit gray counter with up down control and carry Sketch your block diagram design. Clearly label all the signals and connections. For submodules, label port signals inside. a) b) Complete the Verilog codes. Top module only module test_graycodecounter2 (CLOCK 50, KEY,SW, HEXO, LEDG) endmodule

Answer 1

//Qusetion no 2
//2-bit gray code counter
module gray2(clock,reset,up,z,c);

input clock,reset,up;

output [1:0] z;
output c;

//States
parameter S0 = 2'b00,
S1 = 2'b01,
S2 = 2'b11,
S3 = 2'b10;

//Internal Registers
reg [1:0]present_state,next_state;

//Present State Sequential Logic
always@(posedge clock or negedge reset) begin
if(~reset)
present_state <= S0;
else
present_state <= next_state;
end


//Next State Combinational Logic
always@(*) begin
case (present_state)
S0 : begin
if(up)
next_state = S1;
else
next_state = S3;
end
S1 : begin
if(up)
next_state = S2;
else
next_state = S0;
end
S2 : begin
if(up)
next_state = S3;
else
next_state = S1;
end
S3 : begin
if(up)
next_state = S0;
else
next_state = S2;
end
endcase
end

//Output Logic for z
assign z = present_state;

//Output Logic for c;
assign c = (((present_state == S3) && up) || ((present_state == S0) && ~up));

endmodule

//Need 7 segment converter and frequency divider modules for Question no 4
//Requirements for Question 4
//Bcd to Seven Segment Converter
module bcd2seg7(bcd,hex);
//Input port
input [3:0] bcd;
//Output Port
output reg [6:0] hex;

//converting bcd to 7 segment
always @(bcd)
begin
case (bcd) //case statement
0 : hex = 7'b0000001;
1 : hex = 7'b1001111;
2 : hex = 7'b0010010;
3 : hex = 7'b0000110;
4 : hex = 7'b1001100;
5 : hex = 7'b0100100;
6 : hex = 7'b0100000;
7 : hex = 7'b0001111;
8 : hex = 7'b0000000;
9 : hex = 7'b0000100;
//switch off 7 segment when the bcd is not a decimal number.
default : hex = 7'b1111111;
endcase
end

endmodule


//Number of Bits for Scale is not mentioned here taken as 3 bits
//Actually Frequency Divider will have a counter based but as per the question
//it has given to take as scale input. so i have taken directly the formula given.

//Frequency Divider Verilog Code.
module freq_div(clock_in,scale,clock_out);
//Input Port
input clock_in; //input clock
input [24:0]scale; //Scale

//Output Port
output clock_out;

reg [24:0]counter = 25'd0;
reg clk_out = 1'b0;
always@(posedge clock_in) begin
if(counter == scale) begin
counter = 25'd0;
clk_out = ~clk_out;
end
else begin
counter = counter + 1'b1;
end
end

assign clock_out = clk_out;
endmodule

//Requirements Completed

4a)

test-gyaycod conter 2 Clok.50 Clock.out ray 2 clck C. es vesetga up bcd ta Counter seg

//Question 4 b)

//Top module
module test_graycodecounter2(CLOCK_50,KEY0,SW0,HEX0,LEDG0);
//Input ports
input CLOCK_50,KEY0,SW0;

//Output Ports
output [6:0]HEX0;
output LEDG0;

//internal registers and wires
wire clock_out;
wire [24:0]scale;
wire [1:0]z;
//frequency Division from 50 Mhz clock to 1 hz refresh rate

//instantiation of frequency Divider
freq_div FREQ_DIVISION(CLOCK_50,scale,clock_out);

//instantiation of gray code counter
gray2 GRAY_COUNTER(clock_out,KEY0,SW0,z,LEDG0);

//instantiation of bcd to 7 segment converter
bcd2seg7 BCD_TO_7_SEG({2'b00,z},HEX0);

//Remove commented below to check 1 hz refresh rate from 50 mhz
//assign scale = 25000000;

//This will give 50 Mhz clock out if scale = 1.
assign scale = 1;
endmodule




`timescale 1ns/1ns
//Testbench to test Question 4 and simulation for waveforms
module test;
reg CLOCK_50,KEY0,SW0;

wire [6:0]HEX0;
wire LEDG0;

//Instantiation of top module
test_graycodecounter2 DUT(CLOCK_50,KEY0,SW0,HEX0,LEDG0);

//Clock generation for 50 Mhz
always begin
#10 CLOCK_50 = 1'b0;
#10 CLOCK_50 = ~CLOCK_50;
end

//Driving Stimulus
initial begin
#5 KEY0 = 1'b0;
#20 KEY0 = 1'b1;
SW0 = 1'b1;
#300 SW0 = 1'b0;KEY0 = 1'b0;
#20 KEY0 = 1'b1;
#500 $finish;
end
endmodule


//Simulation Waveform

Wave Default test/CLOCK 50 o /test/KEYo /test/SWo 000110 1001111 0000 Sto 000110 1001111 000000 test/HEXO /test/LEDGO