Homework Answers
a)
|
PRESENT STATE |
NEXT STATE |
||||
|
G2 |
G1 |
G0 |
G2+ |
G1+ |
G0+ |
|
0 |
0 |
0 |
0 |
0 |
1 |
|
0 |
0 |
1 |
0 |
1 |
1 |
|
0 |
1 |
0 |
1 |
1 |
0 |
|
0 |
1 |
1 |
0 |
1 |
0 |
|
1 |
0 |
0 |
0 |
0 |
0 |
|
1 |
0 |
1 |
1 |
0 |
0 |
|
1 |
1 |
0 |
1 |
1 |
1 |
|
1 |
1 |
1 |
1 |
0 |
1 |
b)
State Table
|
STATE |
PRESENT STATE |
INPUT |
NEXT STATE |
OUTPUT |
||
|
Q1 |
Q0 |
serial_in |
Q1+ |
Q0+ |
Z |
|
|
S0 |
0 |
0 |
0 |
0 |
0 |
0 |
|
0 |
0 |
1 |
0 |
1 |
0 |
|
|
S1 |
0 |
1 |
0 |
1 |
0 |
0 |
|
0 |
1 |
1 |
0 |
1 |
0 |
|
|
S2 |
1 |
0 |
0 |
0 |
0 |
0 |
|
1 |
0 |
1 |
0 |
1 |
1 |
|
|
UNUSED |
1 |
1 |
0 |
X |
X |
X |
|
1 |
1 |
1 |
X |
X |
X |
|
Add Answer to:
Question 4 State Machines (25 marks) a. (5 marks) A 3-bit Gray code counter advances on...
Finite state machine (FSM) counter design: Gray codes have a useful property in that consecutive numbers differ in only a single bit position. Table 1 lists a 3-bit modulo 8 Gray code representing the...
Finite state machine (FSM) counter design: Gray
codes have a useful property in that consecutive numbers differ in
only a single bit position. Table 1 lists a 3-bit modulo 8 Gray
code representing the numbers 0 to 7. Design a 3-bit modulo 8 Gray
code counter FSM.
a) First design and sketch a 3-bit modulo 8 Gray code counter
FSM with no inputs and three outputs, the 3-bit signal
Q2:0. (A modulo N counter counts from 0 to N −...
Design a Verilog model that describes the following state diagram. (Test bench and simulation are not required) 1. 01 10 1- 10 10 01 01 10 or 01) 01 Design a Verilog model that describes a synchr...
Design a Verilog model that describes the following state diagram. (Test bench and simulation are not required) 1. 01 10 1- 10 10 01 01 10 or 01) 01 Design a Verilog model that describes a synchronous 3 bit counter. The counter has a counting mode control signal (M), when M-o, the counter counts up in the binary sequence, when M- 1, the counter advances through the Gray code sequence. (Test bench and simulation are required to verify the counter...
will give thumbs up need answer asap P3.94pts Implement a 3-bit synchronous gray code down-counter with...
will give thumbs up need answer asap
P3.94pts Implement a 3-bit synchronous gray code down-counter with positive-edge-triggered D flip-flops using graphical symbols of D flip-flops and any logic gates. You can refer to the table below to understand the 3-bit gray code (The desired behavior is as follows: 000 100 101 111 - 110 - 010011001 → 000 → ...). Decimal 1 Gray code 000 001 011 010 110 111 101 100 5 6
1. Design a combinational circuit that coverts a 4-bit Gray code to a 4-bit Excess-3 code....
1. Design a combinational circuit that coverts a 4-bit Gray code to a 4-bit Excess-3 code. Provide detailed solution and explanation 2. Design a double edge-triggered D flip-flop using multiplexers only. The output of the flip-flop Q should "sample" the value of the input D on both rising (+ve) and falling -ve) edges of the clock CLK. Provide detailed solution and explanation 3. Design an FSM counter that counts the sequence: 00, 11, 01, 10, 00, 11, Provide detailed solution...
Write a behavioral Verilog module for a 4-bit Johnson counter that has 8 states. The counter load...
Write a behavioral Verilog module for a 4-bit Johnson counter that has 8 states. The counter loads the "0000" state if reset is low. The counter should start and end with this state. Write a testbench to verify the correctness of the 4-bit Johnson counter. The testbenclh should have a clock with a period of 20ns and a reset signal. The testbench should store the 4-bit binary outputs of the counter in a file, which will be used to provide...
Question 4 State Machines (25 marks) A state machine is required to generate the first 8...
Question 4 State Machines (25 marks) A state machine is required to generate the first 8 digits of pi (ignoring the decimal point) where pi 3.1415926... The output of the state machine must be a 4 bit BCD value representing the current digit, so the state machine output will follow the sequence: 0011 (3), 0001 (1), 0100 (4)... After the final digit in the sequence is output, the state machine must go back to the beginning 3 of 4 and...
please answer question 4 (all parts of question4 please) will rate! 3. (30 pts) Design a 2-bit Gray code generator that ropetitively delivers the sequence 00301911-10-00when the input signal UP-...
please answer question 4 (all parts of question4 please) will
rate!
3. (30 pts) Design a 2-bit Gray code generator that ropetitively delivers the sequence 00301911-10-00when the input signal UP- 1,or in reverse order 009 10기け01 →00→ when UP-0. Your design should include an asynchronous low. active reset operation: the FSM goes to 00 state when a reset signal is applied In addition to the state output z[1). 2[0]. there is a carry/borrow output bit e which is I when...
Can anyone solve this? i dont understand? verilog 1. (30 pts) Design a mod-6 counter. A...
Can anyone solve this? i dont understand? verilog
1. (30 pts) Design a mod-6 counter. A mod-6 counter updates its output per clock rising edge according to the following sequence: 000, 001, 010, 011, 100, 101 (then repeat the pattern....). en is enable control (synchronous high active), resetn is reset control (asynchronous low active signal to reset counting sequence to 000) Complete the following Verilog code: en module mod6(clock, resetn, en, z); zI2:0] clock resetn Endmodule
Question 4 State Machines (25 marks) A state machine is required for a simple vending machine....
Question 4 State Machines (25 marks) A state machine is required for a simple vending machine. The machine takes one dollar coins only. Each time a coin is added the input signal "coin" is set to 1 for one clock cycle When a total of $4 has been added the output signal "deliver" is set to 1 for one clock cycle and the state machine starts counting coins for the next delivery a) (5 marks) Draw a state diagram for...
Use a behavioral Verilog model to design a 3-bit fault tolerant up-down counter. For each flip-fl...
Use a behavioral Verilog model to design a 3-bit fault tolerant up-down counter. For each flip-flop (FF) include asynchronous reset and preset signals. Refer to Example 4.3 on page 160 for an example of a single FF with both reset and preset signals as well as with an enable signal. For this project, you don't need to use FFs with enables. You don't also need not-q (nq) in this assignment. Use active-high signals for reset and present signals. The example...
Finite state machine (FSM) counter design: Gray
codes have a useful property in that consecutive numbers differ in
only a single bit position. Table 1 lists a 3-bit modulo 8 Gray
code representing the numbers 0 to 7. Design a 3-bit modulo 8 Gray
code counter FSM.
a) First design and sketch a 3-bit modulo 8 Gray code counter
FSM with no inputs and three outputs, the 3-bit signal
Q2:0. (A modulo N counter counts from 0 to N −...
Design a Verilog model that describes the following state diagram. (Test bench and simulation are not required) 1. 01 10 1- 10 10 01 01 10 or 01) 01 Design a Verilog model that describes a synchronous 3 bit counter. The counter has a counting mode control signal (M), when M-o, the counter counts up in the binary sequence, when M- 1, the counter advances through the Gray code sequence. (Test bench and simulation are required to verify the counter...
will give thumbs up need answer asap
P3.94pts Implement a 3-bit synchronous gray code down-counter with positive-edge-triggered D flip-flops using graphical symbols of D flip-flops and any logic gates. You can refer to the table below to understand the 3-bit gray code (The desired behavior is as follows: 000 100 101 111 - 110 - 010011001 → 000 → ...). Decimal 1 Gray code 000 001 011 010 110 111 101 100 5 6
1. Design a combinational circuit that coverts a 4-bit Gray code to a 4-bit Excess-3 code. Provide detailed solution and explanation 2. Design a double edge-triggered D flip-flop using multiplexers only. The output of the flip-flop Q should "sample" the value of the input D on both rising (+ve) and falling -ve) edges of the clock CLK. Provide detailed solution and explanation 3. Design an FSM counter that counts the sequence: 00, 11, 01, 10, 00, 11, Provide detailed solution...
Write a behavioral Verilog module for a 4-bit Johnson counter that has 8 states. The counter loads the "0000" state if reset is low. The counter should start and end with this state. Write a testbench to verify the correctness of the 4-bit Johnson counter. The testbenclh should have a clock with a period of 20ns and a reset signal. The testbench should store the 4-bit binary outputs of the counter in a file, which will be used to provide...
Question 4 State Machines (25 marks) A state machine is required to generate the first 8 digits of pi (ignoring the decimal point) where pi 3.1415926... The output of the state machine must be a 4 bit BCD value representing the current digit, so the state machine output will follow the sequence: 0011 (3), 0001 (1), 0100 (4)... After the final digit in the sequence is output, the state machine must go back to the beginning 3 of 4 and...
please answer question 4 (all parts of question4 please) will
rate!
3. (30 pts) Design a 2-bit Gray code generator that ropetitively delivers the sequence 00301911-10-00when the input signal UP- 1,or in reverse order 009 10기け01 →00→ when UP-0. Your design should include an asynchronous low. active reset operation: the FSM goes to 00 state when a reset signal is applied In addition to the state output z[1). 2[0]. there is a carry/borrow output bit e which is I when...
Can anyone solve this? i dont understand? verilog
1. (30 pts) Design a mod-6 counter. A mod-6 counter updates its output per clock rising edge according to the following sequence: 000, 001, 010, 011, 100, 101 (then repeat the pattern....). en is enable control (synchronous high active), resetn is reset control (asynchronous low active signal to reset counting sequence to 000) Complete the following Verilog code: en module mod6(clock, resetn, en, z); zI2:0] clock resetn Endmodule
Question 4 State Machines (25 marks) A state machine is required for a simple vending machine. The machine takes one dollar coins only. Each time a coin is added the input signal "coin" is set to 1 for one clock cycle When a total of $4 has been added the output signal "deliver" is set to 1 for one clock cycle and the state machine starts counting coins for the next delivery a) (5 marks) Draw a state diagram for...
Use a behavioral Verilog model to design a 3-bit fault tolerant up-down counter. For each flip-flop (FF) include asynchronous reset and preset signals. Refer to Example 4.3 on page 160 for an example of a single FF with both reset and preset signals as well as with an enable signal. For this project, you don't need to use FFs with enables. You don't also need not-q (nq) in this assignment. Use active-high signals for reset and present signals. The example...
Most questions answered within 3 hours.
-
Add 1ml of 0.18M of HCl (aq) to 1ml of 0.2M of [Ag(NH3)2]Br
(aq).
Write the...
asked 2 minutes ago -
1. Smoke detectors use Am-241, an alpha emitter, to detect smoke
particles. A parent is concerned...
asked 7 minutes ago -
Scenario: Web application developed to capture customers
demographic and financial information for filling their taxes. This...
asked 10 minutes ago -
Which of the following statements are true?
1. Glass is mostly silicon dioxide and so when...
asked 33 minutes ago -
Korman Company has the following securities in its portfolio of
equity securities on December 31, 2018:...
asked 33 minutes ago -
Using the 12th edition of Language Awareness,
complete the following assignment:
After reading Akiba Solomon's "Thugs....
asked 44 minutes ago -
For all problems assume an effective monthly interest rate of 1%
unless otherwise indicated in the...
asked 55 minutes ago -
Fix all syntax and logical errors for the following program.
Please generate the correct output. //...
asked 1 hour ago -
The USPS sells money orders identified by an 11 –digit number
x1, x2, …, x11. The...
asked 1 hour ago -
Provide an example of equilibrium in relation to
Newton’s First and Second Laws. Explain your answer....
asked 1 hour ago -
You are __________ to commit a Type I error using the 0.05 level
of significance than...
asked 1 hour ago -
1. the following results are obtained:
200
kiwi
575 wild-type
What can we conclude about the...
asked 1 hour ago