Homework Answers
(a)
(b)
|
STATE |
CURRENT STATE |
INPUT |
NEXT STATE |
OUTPUT |
||
|
S1 |
S0 |
coin |
next_S1 |
next_S0 |
deliver |
|
|
VM0 |
0 |
0 |
0 |
0 |
0 |
0 |
|
0 |
0 |
1 |
0 |
1 |
0 |
|
|
VM1 |
0 |
1 |
0 |
0 |
1 |
0 |
|
0 |
1 |
1 |
1 |
0 |
0 |
|
|
VM2 |
1 |
0 |
0 |
1 |
0 |
0 |
|
1 |
0 |
1 |
1 |
1 |
0 |
|
|
VM3 |
1 |
1 |
0 |
1 |
1 |
0 |
|
1 |
1 |
1 |
0 |
0 |
1 |
|
(c)
|
CURRENT STATE |
INPUT |
NEXT STATE |
||||||
|
vm3 |
vm2 |
vm1 |
vm0 |
coin |
next_vm3 |
next_vm2 |
next_vm1 |
next_vm0 |
|
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
1 |
|
0 |
0 |
0 |
1 |
1 |
0 |
0 |
1 |
0 |
|
0 |
0 |
1 |
0 |
0 |
0 |
0 |
1 |
0 |
|
0 |
0 |
1 |
0 |
1 |
0 |
1 |
0 |
0 |
|
0 |
1 |
0 |
0 |
0 |
0 |
1 |
0 |
0 |
|
0 |
1 |
0 |
0 |
1 |
1 |
0 |
0 |
0 |
|
1 |
0 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
|
1 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
1 |
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Question 4 State Machines (25 marks) A state machine is required for a simple vending machine....
Question 4 State Machines (25 marks) A state machine is required to generate the first 8...
Question 4 State Machines (25 marks) A state machine is required to generate the first 8 digits of pi (ignoring the decimal point) where pi 3.1415926... The output of the state machine must be a 4 bit BCD value representing the current digit, so the state machine output will follow the sequence: 0011 (3), 0001 (1), 0100 (4)... After the final digit in the sequence is output, the state machine must go back to the beginning 3 of 4 and...
Question 4 State Machines (25 marks) a. (5 marks) A 3-bit Gray code counter advances on...
Question 4 State Machines (25 marks) a. (5 marks) A 3-bit Gray code counter advances on positive clock edges and generates outputs in the sequence: 000, 001, 011, 010, 110, 111, 101, 100. Draw the assigned state table for a state machine implementing this counter. b. (10 marks) For the Gray code counter in part a, derive (unoptimised) equations for the next state as a function of the current state. c. (10 marks) Consider the following sequence detector. In each...
The California student chapter is co-sponsoring a tea vending machine with a heavily subsidized price of...
The California student chapter is co-sponsoring a tea vending machine with a heavily subsidized price of 15 cents a cup. Design a Mealy FSM for the vending machine assuming the students can load nickels (input N) and dimes (input D), only one coin at a time. If the user tries to enter two coins at the same time, the vending machine would not allow it, i.e. it will stay in the same state. If the user pays more than 15...
3. Finite State Machine. Using a ROM based finite state machine (FSM), design a bi-directional repetitive...
3. Finite State Machine. Using a ROM based finite state machine (FSM), design a bi-directional repetitive 3-bit modulo-6 (0,1,2,3,4,5) counter (see Table 3). The design has one input named Dir and three outputs named B2, B1 and BO. The outputs (B2, B1 and BO) are dependent upon being in the present state only. After each clock pulse, when Dir is at logic "O', the outputs (B2, B1, BO) step through the count sequence in following order:- 0,1,2,3,4,5. After each clock...
how slove 4-34, 4-35, 4-36??? I dont know that! please hlep me! 306 □ CHAPTER 4/SEQUENTIAL CIRCUITS OTABLE 4-16...
how slove 4-34, 4-35, 4-36??? I dont know that! please hlep me!
306 □ CHAPTER 4/SEQUENTIAL CIRCUITS OTABLE 4-16 State Table for Problem 4-33 Next State Input Output Present State 4-36 4-37 0 0 0 0 4-38 Design the circuit specified by Table 4-14 and use the sequence from Problen 4-31 (either yours or the one posted on the text website) to perform an automatic logic simulation-based verification of your design. 4 433. The state table for a sequential circuit...
1. (50 POINTS) A divide-by-N counter is a special type of a counter with one output...
1. (50 POINTS) A divide-by-N counter is a special type of a counter with one output and no inputs. The output Y is high for one clock cycle out of every N, i.e. the output divides the clock frequency by N. As an example, the waveform for a divide-by-3 counter and the corresponding FSM for this counter are shown below S1 Y. O S2 Y. O SO Now, consider a divide-by-4 counter to answer the following I.A.) (5 POINTS) Draw...
4. Create a 1-hot implementation of the traffic light state machine from problem #2 (a) Create the state table with state assignments, showing the next states as a function of the input and the outpu...
4. Create a 1-hot implementation of the traffic light state machine from problem #2 (a) Create the state table with state assignments, showing the next states as a function of the input and the outputs as a function of the present state. (b) Determine the logic equations for the next state inputs to the flops, and for the six output control signals.
4. Create a 1-hot implementation of the traffic light state machine from problem #2 (a) Create the state...
5) Decoders: Given the following circuit, S0 and S1 are computed using a 4-2 priority encoder with the priorities indicated on the figure. (hint: IDLE signal is always 0, if any of the inputs...
5) Decoders: Given the following circuit, S0 and S1 are computed using a 4-2 priority encoder with the priorities indicated on the figure. (hint: IDLE signal is always 0, if any of the inputs 10,11,12, or 13 is 1) 6 points) 4-to-2 Priority Encoder 10 YO YI 13 IDLE 13> 11 > 12>10 12 Full c Adder So Fill the following table showing the output signals S0 and SI given the input signals w, x, y, a) and z. Prof...
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Design a 4-bit serial bit sequence detector. The input to your state detector is called DIN...
Design a 4-bit serial bit sequence detector. The input to your state detector is called DIN and the output is called FOUND. Your detector will assert FOUND anytime there is a 4-bit sequence of "0101". For all other input sequuences the output is not asserted. (a) (b) Provide the state diagram for this FSM. Encode your states using binary encoding. How many D-Flip-Flops does it take to implement the state memory for this FSM? (c) Provide the state transition table...
Question 4 State Machines (25 marks) A state machine is required to generate the first 8 digits of pi (ignoring the decimal point) where pi 3.1415926... The output of the state machine must be a 4 bit BCD value representing the current digit, so the state machine output will follow the sequence: 0011 (3), 0001 (1), 0100 (4)... After the final digit in the sequence is output, the state machine must go back to the beginning 3 of 4 and...
Question 4 State Machines (25 marks) a. (5 marks) A 3-bit Gray code counter advances on positive clock edges and generates outputs in the sequence: 000, 001, 011, 010, 110, 111, 101, 100. Draw the assigned state table for a state machine implementing this counter. b. (10 marks) For the Gray code counter in part a, derive (unoptimised) equations for the next state as a function of the current state. c. (10 marks) Consider the following sequence detector. In each...
The California student chapter is co-sponsoring a tea vending machine with a heavily subsidized price of 15 cents a cup. Design a Mealy FSM for the vending machine assuming the students can load nickels (input N) and dimes (input D), only one coin at a time. If the user tries to enter two coins at the same time, the vending machine would not allow it, i.e. it will stay in the same state. If the user pays more than 15...
3. Finite State Machine. Using a ROM based finite state machine (FSM), design a bi-directional repetitive 3-bit modulo-6 (0,1,2,3,4,5) counter (see Table 3). The design has one input named Dir and three outputs named B2, B1 and BO. The outputs (B2, B1 and BO) are dependent upon being in the present state only. After each clock pulse, when Dir is at logic "O', the outputs (B2, B1, BO) step through the count sequence in following order:- 0,1,2,3,4,5. After each clock...
how slove 4-34, 4-35, 4-36??? I dont know that! please hlep me!
306 □ CHAPTER 4/SEQUENTIAL CIRCUITS OTABLE 4-16 State Table for Problem 4-33 Next State Input Output Present State 4-36 4-37 0 0 0 0 4-38 Design the circuit specified by Table 4-14 and use the sequence from Problen 4-31 (either yours or the one posted on the text website) to perform an automatic logic simulation-based verification of your design. 4 433. The state table for a sequential circuit...
1. (50 POINTS) A divide-by-N counter is a special type of a counter with one output and no inputs. The output Y is high for one clock cycle out of every N, i.e. the output divides the clock frequency by N. As an example, the waveform for a divide-by-3 counter and the corresponding FSM for this counter are shown below S1 Y. O S2 Y. O SO Now, consider a divide-by-4 counter to answer the following I.A.) (5 POINTS) Draw...
4. Create a 1-hot implementation of the traffic light state machine from problem #2 (a) Create the state table with state assignments, showing the next states as a function of the input and the outputs as a function of the present state. (b) Determine the logic equations for the next state inputs to the flops, and for the six output control signals.
4. Create a 1-hot implementation of the traffic light state machine from problem #2 (a) Create the state...
5) Decoders: Given the following circuit, S0 and S1 are computed using a 4-2 priority encoder with the priorities indicated on the figure. (hint: IDLE signal is always 0, if any of the inputs 10,11,12, or 13 is 1) 6 points) 4-to-2 Priority Encoder 10 YO YI 13 IDLE 13> 11 > 12>10 12 Full c Adder So Fill the following table showing the output signals S0 and SI given the input signals w, x, y, a) and z. Prof...
Design a 4-bit serial bit sequence detector. The input to your state detector is called DIN and the output is called FOUND. Your detector will assert FOUND anytime there is a 4-bit sequence of "0101". For all other input sequuences the output is not asserted. (a) (b) Provide the state diagram for this FSM. Encode your states using binary encoding. How many D-Flip-Flops does it take to implement the state memory for this FSM? (c) Provide the state transition table...
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