Question

Can anyone solve this? i dont understand? verilog

1. (30 pts) Design a mod-6 counter. A mod-6 counter updates its output per clock rising edge according to the following sequence: 000, 001, 010, 011, 100, 101 (then repeat the pattern....). en is enable control (synchronous high active), resetn is reset control (asynchronous low active signal to reset counting sequence to 000) Complete the following Verilog code: en module mod6(clock, resetn, en, z); zI2:0] clock resetn Endmodule

Answer 1

//design

module mod6 (clock, resetn, en, z);

input clock, resetn, en;

output [2:0] z;

reg [2:0] count;

always @ (posedge clock, resetn)

begin

   if (~resetn)

       count <= 3'b000;

   else

        if (en)

           count <= count + 1;

end

assign z = count;

endmodule

/////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////

//Testbench

module tb_mod6 ();

reg clock, resetn, en;

wire [2:0] z;

mod6 uut (clock, resetn, en, z);

always #10 clock = ~clock;

initial

begin

   clock = 0;

   resetn = 0;

   en = 1;

   #20;

   resetn = 1;

   en = 0;

   #40;

   en = 1;

end

endmodule

////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////

//Simulation

E Wave File Edit View Add Format Tools Bookmarks Window Help Wave -Default Msgs /tb_mod6jdock /tb modé/en 400 450 Oursor 1 45 ps 0 ps to 516 ps 1:02 PM 5/6/2019 O Type here to search