Question

Use a behavioral Verilog model to design a 3-bit fault tolerant up-down counter. For each flip-flop (FF) include asynchronous reset and preset signals. Refer to Example 4.3 on page 160 for an example of a single FF with both reset and preset signals as well as with an enable signal. For this project, you don't need to use FFs with enables. You don't also need not-q (nq) in this assignment. Use active-high signals for reset and present signals. The example shows active-low signals (e.g.,_reset or_preset with an underscore indicates active-low). Also label each reset and preset signals with different names such as defining these signals as vectors. For example. "reg[4:0] reset, preset;" defines 5 bits reset and preset signals. You can reset all the FFs by setting reset 5b11111 and preset 5b00000; you can reset FF0 (bit q0) with reset-5'b00001 and preset-5'b00000; or preset FF1 (bit q1) with reset- 5'b00000 and preset-5'b00010 assume active-high reset and preset signal. Also, you would need to clock manually. That is, the following Verilog statements will clock the counter twice assuming positive-edge FFs. l.k0 #5 clk-1; #5 clk-0; #5 clk 1; 1) Reset the counter and clock until the counter becomes 3 (counter bits are q2q1q0 2) Cause a fault at g0 by resetting qo. I.e., this will cause counter value to change from 3 to 2 (q2q1q0 010) 3) Clock the counter, if your circuit is working correctly, the counter should advance to 4 (q2q1q0 100) 4) Cause a fault at q1. This should make q2q1q0 110. 5) Clock the counter. If your circuit is working correctly, the counter should advance to 5 (q2q10 101). 6) Advance the counter to 7 (q2q1q0 111) by clocking twice 7) Cause a fault at q2. This should make q2q1q0 011 8) Clock the counter. If you counter is working correctly, the counter should advance to 0. 9) Switch the counter to count down and clock twice. The counter show 6 (q2q1q0 110) 10) Cause a fault at q0. This should make q2q1q0 111 11) Clock the counter. If you counter is working correctly, the counter should decrement to 5 (q2q1q0 101) 12) You may add additional test cases of your own. Report: Submit the followings: (30pts) Hand design solution for the mod-8 up/down counter (i.e., the FSD, the FSM block diagram showing FFs and NSG and OG as blocks. a) b) Fault tolerant design as you did in HW2. c)Print out of the Verilog models-Put your names as a comment in the code. (The screenshot of the output, you names must be printed on the output files (i.e., use Sdisplay to print your names) output and show that it matches with the generated results, if not explain).

Answer 1

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