Question

please solve the question completely and show the steps ... thumb up will be given

(5 points each) [CO: 6] a. If RO and R1 are both 16-bit serial shift registers, each with a single serial input (S_IN) and a single serial output (S_OUT), clock and reset. Design using RO and Rl additional logic, a circuit that would store the output S_OUT of either RO or Rl into a D-FF based on input CH. If CH is 0, S OUT of RO will be stored in the D-FF (at the edge of the clock) and if CH is 1, S_OUT of RI will be stored in the D-FF (at the edge of the clock). Show all connections. B. Draw a 2-Bit ripple counter using T-FFs. Label the FF outputs C1C0, where C1 is the most significant bit. Make sure you appropriately and clearly label all inputs/outputs, CLK, reset, etc. C. Given two D-FFs, FF1 and FFo, two 4x1 multiplexers, four 2-bit registers (RO, R1, R2, and R3: oth narallel outputs) and no additional logic gates, design a circuit to support the following M1 MO0 values operations based on 2-bit inputs M1 and MO: Operation (at the rising edge of the clock) ROFFI FFO (bits of RO stored in FF1 & FFO) 0 1 1 0 RIFFI FFO (bits of R1 stored in FFI& FFO R2-FF1 FFO (bits of R2 stored in FFI&FFO R3FF1 FFO (bits of R3 stored in FF1 &FFO Design a 2-bit synchronous binary counter that counts-down when the input D- 1 and counts up when D 0 (no need to draw the circuit, only derive the flip-flop equations) d.

Answer 1

Given Ro, RI a16 bfl Serlal shift se wilh Scial nput (S and oulput(S-OUT hese oufputs fom each ShiR cgstess are o弋ese,Ropope.rta oEos?tive -k Aseavne edge trfgewng clock SDUT lock rese PFF Leset Mox CLK output RI shit egisiee S-out S TN circuit diagram c咯8esfoned 6lock e Co

which ae deed m Lt stale table

clock 1 O outpuh Cik Rafi)ezd FFO Mf MO cựcu. da

*t has &nput o' and fes operates în up ldoun o ac up Counter 2 bie Counte ave autputs ony and hven fh síale dliaghavm 'The State PosstoLo States ane u-poM resel lf state d?a안의am The Stale are mothing^ lt oututs Counter