Use the Quartus Prime Text Editor to implement a behavioral model of the D flip-flop described above in a file named d_flops.sv. Specify the D flip-flop’s module according to the interface specification given in the table below.
Port |
Mode |
Data Type |
Size |
Description |
RST |
in |
logic |
1-bit |
Active high asynchronous reset |
CLK |
in |
logic |
1-bit |
Synchronizing clock signal |
EN |
in |
logic |
1-bit |
Synchronous clock enable |
D |
in |
logic |
1-bit |
Synchronous data input |
Q |
out |
logic |
1-bit |
Current/present state |
Qbar |
out |
logic |
1-bit |
Inverted current/present state |
Within the module implementation, model the D flip-flop using the following modeling specifications:
Declare an intermediate signal named Qtemp of type logic. Signal Qtemprepresents the current state of the D flip-flop.
Utilize a concurrent sensitivity-list always_ff @ ( ) statement to represent the behavior of the D flip flop. Which signal(s) should be included in the sensitivity list?(Don’t forget to enclose this in a begin – end block if needed)
Within the sensitivity list, detect the rising edge of port signals CLK and RST using the keyword posedge. See the example below:
always_ff @(posedge name_signal)
Within the implementation portion of the always @ statement, use nestedsequential if statements to model the behavior of the D flip-flop. What signal(s), if any, have priority? (Don’t forget to enclose this in a begin – end block if needed)
Properly assign port signals Q and Qbar.
//D Flip Flop in SV
module d_flop(
input logic RST,CLK,EN,D, //Input port Declaration
output logic Q,Qbar //Output port Declaration
);
logic Qtemp; //Internal Variable
//Sequential BLOCK using nested if
always_ff @(posedge CLK or posedge RST) begin
if(RST) //Set = 1 or posedge of RST
Qtemp <= 1'b0;
else if(EN) //EN = 1
Qtemp <= D;
else //EN = 0, HOLD previous value
Qtemp <= Qtemp;
end
//Assigning Output Ports
assign Q = Qtemp;
assign Qbar = ~Qtemp;
endmodule
//Testbench in SV
module test;
logic RST,CLK,EN,D,Q,Qbar;
//Instantiation of D Flip Flop
d_flop DFF(RST,CLK,EN,D,Q,Qbar);
//Driving Clock
always begin
#5 CLK = 1'b0;
#5 CLK = ~CLK;
end
//Driving Stimulus
initial begin
RST = 1'b1;
@(posedge CLK) RST = 1'b0;
EN = 0; D = 0;
@(posedge CLK) EN = 0; D = 1;
@(posedge CLK) EN = 1; D = 1;
@(posedge CLK) EN = 1; D = 0;
@(posedge CLK) EN = 1; D = 1;
@(posedge CLK) EN = 0; D = 0;
@(posedge CLK) EN = 1; D = 1;
@(posedge CLK) $finish;s
end
endmodule
//Simulation Waveform
//Quartus Synthesis
Use the Quartus Prime Text Editor to implement a behavioral model of the D flip-flop described ab...
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