Question

The schematic of a positive edge-triggered 4-bit, parallel-in, parallel-out data register active high asynchronous reset is below. shown below. Study the schematic and perform the procedure RST D RST Q EN HEN 아 →ID RST Q CLK EN FF3 --D RST FF2 CLK FF1 CLK EN 14-bit Data : Register FFO

Use the Quartus Prime Text Editor to implement a structural model of the 4-bit data register shown above in a file named reg_4bit.sv. Specify the 4-bit data register’s module according to the interface specification given in the table below.

Port	Mode	Data Type	Size	Description
RST	in	logic	1-bit	Active high asynchronous reset
CLK	in	logic	1-bit	Synchronizing clock signal
EN	in	logic	1-bit	Synchronous clock enable
D	in	logic vector	4-bits	Synchronous data input
Q	out	logic vector	4-bits	Current/present state (data) stored by the register.
Qbar	out	logic vector	4-bits	Inverted current/present state (data) stored by the register.

Within the declaration portion of the module, perform the following declarations:

Declare a constant named REG_WIDTH (using ALL CAPS) of type integer and assign it to 4. See the example shown below.

                         localparam REG_WIDTH = 4;

Within the implementation portion of the module, model the parallel-in, parallel-out data register according to the following modeling specifications:

• Use a concurrent for-generate statement with the following attributes:o AgeneratelabelnamedFF_stages

• A generate parameter named k

• A range that includes constant REG_WIDTH and a down to direction.

o A generate body that uses a concurrent module instantiationstatement to instantiate the D flip-flops. Use an instance label named FFand associate the ports of the instances using named association.

Answer 1

// RTL code in System verilog

//D Flip Flop in SV

module d_flop(

input logic RST,CLK,EN,D, //Input port Declaration

output logic Q,Qbar //Output port Declaration

);

logic Qtemp; //Internal Variable

//Sequential BLOCK using nested if

always_ff @(posedge CLK or posedge RST) begin

if(RST) //Set = 1 or posedge of RST

Qtemp <= 1'b0;

else if(EN) //EN = 1

Qtemp <= D;

else //EN = 0, HOLD previous value

Qtemp <= Qtemp;

end

  

//Assigning Output Ports

assign Q = Qtemp;

assign Qbar = ~Qtemp;

endmodule

//Data Register code in SV

module data_register(RST,CLK,EN,D,Q,Qbar);

localparam REG_WIDTH = 4;

input logic RST,CLK,EN; //Input port Declaration

input logic [REG_WIDTH-1:0]D; //Data Input port Declaration

output logic [REG_WIDTH-1:0]Q,Qbar; //Output port Declaration

// D flip flop Instantiation using generate loop based on local parameter

generate

genvar k;

for(k=0 ; k<REG_WIDTH ; k++)

begin : DFF_Instance

d_flop DFF(RST,CLK,EN,D[k],Q[k],Qbar[k]);

end

endgenerate

endmodule

//Testbench in SV

module test;

logic RST,CLK,EN;

logic [3:0]D,Q,Qbar;

//Instantiation of Data Register

data_register DATA_REGISTER(RST,CLK,EN,D,Q,Qbar);

//Driving Clock

always begin

#5 CLK = 1'b0;

#5 CLK = ~CLK;

end

  

//Driving Stimulus

initial begin

RST = 1'b1;

@(posedge CLK) RST = 1'b0;

EN = 0; D = 0;

@(posedge CLK) EN = 0; D = 9;

@(posedge CLK) EN = 1; D = 10;

@(posedge CLK) EN = 1; D = 0;

@(posedge CLK) EN = 1; D = 15;

@(posedge CLK) EN = 0; D = 0;

@(posedge CLK) EN = 1; D = 9;

@(posedge CLK) EN = 0;

@(posedge CLK) $finish;

end

endmodule

//Simulation Waveform

M Modelsim PE Student Edition 104 File Edit View Compile Simulete Add Wave Tools Layout BookmarksWindow Help 凸庬 elave-Default test,RST test/aK test EN test 1ho 1ho 4h9 -Fo 90 ns 40 Cursor 1 75邝 ETrascript -Wave R cbectsT irar--sm-Edata register.sv Now: 90 ns Delta: 1 sit/test/eDUTIAL #58 11ns to 95 ns

// QUARTUS synthesis

n Report data register Flow Summary Entityinstance of Contents Cyclone Ⅳ E: AUTO data_ register Flow Summary Flow Settings Flow Non-Default Global Settings Flow Elapsed Time Flow OS Summary Flow Log D Successful Mon Mar 25 12:08:32 2019 18.0.0 Build 614 04/24/2018 SJ ite Edition data register data register Cyctone rVE Flow Status Quartus Prime Version Revislon Name Top-level Entity Name Family Total logic elements Total registers Total pins Total virtual pins Total memory bits D Analysls & Synthesis Flow Messages 15 0 0 Find 00 Find Next Type ID Message 28030 Paralle compilation is enabled and wiLl use 12 or the 32 processors detected 12021 Found 3 design units, including 3 entities, in source file pipo.sv 12127 Elaborating entity "data register for the top levei hierarchy 12128 Elaborating entity "d flop" for hierarchy "d flop: DFF instancee1.DFF" 286030 Tining-Driven Synthesis 1s unning > 16810 Generating hard block part1t1on "hard-block:auto generated nst" . 21057 Implemented le device resources after synthesis . the final resource count might be dlfferent Quartus Prime Analysis & Synthesis was successful. θ errors, 1 warning

// RTL SCHEMATIC OBTAINED FROM QUARTUS SYNTHESIS

d ropsiorr instanceloj.DrFi CLK CLU 0 Qbar Obar3.0] D 에 EN RST d flop.DFF instancel1].DFF CLK Obar EN d flop:DFF Instance 2].DFF 2 Qbar EN RST d flop DFF Instance(3).DFF EN