Question

How do I change these modules so that the communication is bidirectional (inout)? I'm simply not sure how to modify the code. I know i need to add an inout port but I don't know how to do it. I have watched multiple tutorials but I can't figure it out.

module mem(
input logic clk, we , // write enable bit, active low
input logic [n-1:0] in ,
input logic [m-1:0] addr ,
output logic [n-1:0] out ) ;
parameter n = 1, m = 1, k = 1 << m ; //data width, address width, size
logic [n-1:0] memo [k-1:0] ;
// array of 2^m elements, each being an n-bit wide register
assign out = memo[addr] ;
always_ff @(posedge clk) begin
if (! we ) memo[addr] = in ;
end
endmodule

-----------------------------

module stack(
input logic clk , rst , // clock and reset
input logic [1:0] op , //operation PUSH or POP (one-hot)
input logic [n-1:0] pushval , // PUSH argument
output logic [n-1:0] popval ) ; // POP result
parameter n = 1, m = 1, k = 1<< m ; // data width, address width, size
logic [m-1:0] addr ; // address for memory
logic up, down ; // breaking op down to 2 separate bits
logic [n-1:0] in ; // input for memory
logic [n-1:0] out ; // output from memory
logic we ; // write enable signal for memory
logic [m-1:0] addr1 ; // counter output
assign up = (addr == {m{1'b1}}) ? 1'b0 : op[1] ;
assign down = (addr == {m{1'b0}}) ? 1'b0 : op[0] ;
assign in = (op == 2'b10) ? pushval : {n{1'b0}};
assign we = rst ? 1'b1 : !(up ^ down) ;
assign addr = (op == 2'b10) ? addr1 + 1'b1 : addr1 ;
// instantiate memory module
  
mem #(n,m,k) memory(clk, we, in, addr, out) ;
  
assign popval = out ;
// instantiate counter module
  
udl #(m) counter(clk, rst, up, down, addr1) ;
  
endmodule

Answer 1

I am just told to redesign the modules so that the data communication takes place through a bidirectional bus connection.