Question

A sequential circuit has one input (X), a clock input (CLK), and two outputs (S and V). X, S and V are all one-bit signals. X represents a 4-bit binary number N, which is input least significant bit first. S represents a 4-bit binary number equal to N + 3, which is output least significant bit first. At the time the fourth input occurs, V = 1 if N + 3 is too large to be represented by 4 bits; otherwise, V = 0. The value of S should be the proper value, not a don’t care, in both cases. The circuit always resets after the fourth bit of X is received. For simplicity, assume the sequential circuit is implemented with the following state table. The outputs are (S,V). All state changes occur on the falling edge of the clock pulse. For simplicity, you can just follow the following table for your code.

Present State	Next State	Next State	Output	Output
	X=0	X=1	x=0	x=1
S0	S1	S2	1,0	0,0
S1	S3	S4	1,0	0,0
S2	S4	S4	0,0	1,0
S3	S5	S5	0,0	1,0
S4	S5	S6	1,0	0,0
S5	S0	S0	0,0	1,0
S6	S0	S0	1,0	0,1

Write A Verilog Description using the State Table Shown Above.

The following code should be helpful guide to your lab (You need to make modifications, this code is for illustration purpose only) 6. module controllerl (x,clk, rstn,y,z); input x; input clk; input rstn; output y; output Z; parameter S03'h0, S1 -3'hl, S23'h2, S3 3'h3, S4 3'h4; reg [2:0] PRState, NXState reg y; assign Zy: always e (PRState) begin if (PRState-S4) y else y 1'b0; 1'b1; end always (posedge clk or negedge rstn) begin if (rstn1'b0) PRState SO; else PRStateNXState; end always (PRState or x) begin case (PRState) else NXS tate = S0; else NXS tate = S1; else NXState = S2; else NXState-S3; S4: NXState-S4; endcase endmodule

Answer 1

I've write down the the VLSI code in notepad as right now I don't have the software, you can check the code if its is correct, I think it will work.