Question

Given the following verilog code, draw the corresponding state diagram for it.

module mysterious
(input reset, clk, TB, TA,

output reg [1:0] LB, LA);

reg [1:0] cstate, nstate;

parameter S0 = 2'b00;

parameter S1 = 2'b01;

parameter S2 = 2'b10;

parameter S3 = 2'b11;

parameter grn = 2'b00;

parameter ylw = 2'b01;

parameter rd = 2'b10;

// state register
always @ (posedge clk, posedge reset) begin

if (reset) cstate <= S0;

else cstate <= nstate; end

// next state logic always @ (*) begin

case (cstate) S0: if (~TA)

nstate = S1;

else nstate = S0;

S1: nstate = S2; S2: if (~TB)

else S3:

default: endcase

end

nstate = S3; nstate = S2; nstate = S0; nstate = S0;

// output logic always @ (*) begin

if (cstate == S0) begin LB = rd;

LA = grn;

end

else if (cstate == S1) begin LB = rd;

LA = ylw;

end

else if (cstate == S2) begin LB = grn;

LA = rd;

end

else begin LB = ylw;

LA = rd;

3

end end

endmodule

Answer 1