How do I create a testbench with the verilog code below? module ganada(Clk, U1, D2, U2,...
How do I create a testbench with the verilog code below?
module ganada(Clk, U1, D2, U2, D3, U3, D4, F1, F2, F3, F4, CF, S);
input Clk, U1, D2, U2, D3, U3, D4, F1, F2, F3, F4;
output [6:0] CF, S;
reg [6:0] CF, S;
reg [1:0] SS, B, NS;
initial begin
NS=2'b00; SS=2'b00;
end
always@(posedge Clk) begin
case(NS)
2'b00: CF=7'b1111001;
2'b01: CF=7'b0100100;
2'b10: CF=7'b0110000;
2'b11: CF=7'b0011001;
endcase
case(SUD)
2'b00: S=7'b1000000;
2'b01: S=7'b1111001;
2'b10: S=7'b0100100;
default: S=7'b0000000;
endcase
if(U1==1 || F1==1) begin
B=2'b00;
end
if(D2==1 || U2==1 || F2==1) begin
B=2'b01;
end
if(D3==1 || U3==1 || F3==1) begin
B=2'b10;
end
if(D4==1 || F4==1) begin
B=2'b11;
end
if(NS==B) begin
SS=2'b00;
end
else if(NS<B) begin
SS=2'b01;
end
else if(NS>B) begin
SS=2'b10;
end
if(SS==2'b01) begin
if(NS<B) begin
SS=2'b01;
end
else if(NS==B) begin
SS=2'b00;
end
end
if(SS==2'b10) begin
if(NS>B) begin
SS=2'b10;
end
else if(NS==B) begin
SS=2'b00;
end
end
if(SS==2'b00) begin
NS=NS;
end
else if(SS==2'b01) begin
NS=NS+1;
end
else if(SS==2'b10) begin
NS=NS-1;
end
end
endmodule
Homework Answers
Given code has a syntax mistake so code modified as below;
module ganada(Clk, U1, D2, U2, D3, U3, D4, F1, F2, F3, F4, CF, S);
input Clk, U1, D2, U2, D3, U3, D4, F1, F2, F3, F4;
output [6:0] CF, S;
reg [6:0] CF, S;
reg [1:0] SS, B, NS;
initial begin
NS=2'b00; SS=2'b00;
end
always@(posedge Clk) begin
case(NS)
2'b00: CF=7'b1111001;
2'b01: CF=7'b0100100;
2'b10: CF=7'b0110000;
2'b11: CF=7'b0011001;
endcase
// in sensitivity list of given code u mentioned SUD which is not at all defined,and as per logic i understand here internal register SS is defined in case statement sensitivity list.
case(SS)
2'b00: S=7'b1000000;
2'b01: S=7'b1111001;
2'b10: S=7'b0100100;
default: S=7'b0000000;
endcase
if(U1==1 || F1==1) begin
B=2'b00;
end
if(D2==1 || U2==1 || F2==1) begin
B=2'b01;
end
if(D3==1 || U3==1 || F3==1) begin
B=2'b10;
end
if(D4==1 || F4==1) begin
B=2'b11;
end
if(NS==B) begin
SS=2'b00;
end
else if(NS<B) begin
SS=2'b01;
end
else if(NS>B) begin
SS=2'b10;
end
if(SS==2'b01) begin
if(NS<B) begin
SS=2'b01;
end
else if(NS==B) begin
SS=2'b00;
end
end
if(SS==2'b10) begin
if(NS>B) begin
SS=2'b10;
end
else if(NS==B) begin
SS=2'b00;
end
end
if(SS==2'b00) begin
NS=NS;
end
else if(SS==2'b01) begin
NS=NS+1;
end
else if(SS==2'b10) begin
NS=NS-1;
end
end
endmodule
//verilog testbench code for given module
module testbench;
// input and output declarations
reg Clk, U1, D2, U2, D3, U3, D4, F1, F2, F3, F4;
wire [6:0] CF, S;
// instantiate device under test (DUT)
ganada DUT (Clk, U1, D2, U2, D3, U3, D4, F1, F2, F3, F4, CF, S);
// clock defined with 10 ns period
initial begin
Clk =0;
forever #5 Clk=~Clk;
end
// random input stimuli given in below block( all inputs are applied in some of different cases with different values)
initial begin
$dumpfile ("dump.vcd");
$dumpvars;
U1 = 0; D2=0; U2=0;D3=0;U3=0;
D4=0; F1=0; F2=0;F3=0; F4=0;#5;
U1 = 0; D2=1; U2=0;D3=1;U3=0;
D4=0; F1=0; F2=0;F3=0; F4=0;#5;
U1 = 0; D2=0; U2=1;D3=0;U3=1;
D4=0; F1=1; F2=0;F3=0; F4=0;#5;
U1 = 0; D2=0; U2=1;D3=1;U3=0;
D4=1; F1=1; F2=1;F3=1; F4=1;#5;
U1 = 1; D2=1; U2=1;D3=1;U3=1;
D4=0; F1=1; F2=0;F3=0; F4=1;#5;
U1 = 1; D2=1; U2=0;D3=1;U3=0;
D4=1; F1=0; F2=1;F3=0; F4=1;#5;
U1 = 1; D2=0; U2=1;D3=0;U3=1;
D4=0; F1=1; F2=0;F3=1; F4=1;#5;
U1 = 0; D2=1; U2=0;D3=1;U3=0;
D4=1; F1=0; F2=0;F3=0; F4=0;#5;
U1 = 1; D2=1; U2=1;D3=1;U3=1;
D4=1; F1=0; F2=1;F3=0; F4=0;#5;
U1 = 0; D2=0; U2=0;D3=0;U3=0;
D4=1; F1=1; F2=1;F3=1; F4=1;
#5 $finish;
end
endmodule
// Simulation waveforms
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