Question

I am making a 4-bit universal shift register that can perform right shift, left shift, and parallel loading using 4-to-1 multiplexers in VHDL. I keep getting red lines for u3, u2, u1, u0. The error says the following below. What is wrong with my code? How can I fix it?

librarviees, use ieee.std_logic_1164.all; entity uni shift.reg.is porti 1 : in std. Jogis vector (3 downto.0); I, w, clock : in std logici 9: buffer std. Jogis vector (3 downto 0)); end uni shift.reg architecture behavioral of uni shift.reg.is component muxdtt perti do, d1, d2, d3, clock in std.logis seli instd logis.vector(1 downto); 9 : out std logis); end component; begin Bi muxdit port mapw,r(3), I, clock, 9(3)); uw muxoft port maple(3), (2), I, clock, 9(2)); ti muxoff port mapla(2), r(1),1, clock, 9(1)); li muxoff port map(9(1),r(0), 1, clock, 9(0)); end behavioral; librarvises use ieee.std_logic_1164.all; entity muxdiff is do, d1, d2, d3, clock in std.logis seli in std logis.vector(1 downto 0); 9 : out std logic); end muxdi. architecture behavior of muxdff is begin begin wait until clock'event and clock ='1'; if sel = "00" then