Question

(15 points) Your colleague is trying to code a VHDL model for a 7419 register. Review the code on the next page and make any and all correction correct working model. Note the function model. Note the function table and additional information regarding need to solve this problem. DL model for a 74194 4-bit bidirectional universal shift tions that are necessary to produce a al information regarding the problem that you Control Signals Mode CirN SI SO Outputs 1 1 1 0 0 1 0 1 0 0 Q3 RSIN Q2 D3 0 0 Q2 Q Q3 Q2 Qi Qo D2 Di 0 (asynchronous clear) Qo (hold) 01 (right shift) LSIN (left shift) Do (parallel load) 1 1 1 Notes: 1. S1 and SO control the mode of the shift register as described in the table above. 2. RSIN is the bit shifted in for the right shift operation and LSIN is the bit shifted in for the left shift operation

Answer 1

soluion;:

given data:

The code have been corrected for errors and given below

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.numeric_std.ALL;
-- Entity Definition starts here
entity e74194 is
port (S1, S0, Clrn, RSIN, LSIN, clk : in std_logic; D: in std_logic_vector (3 downto 0); -- All th input ports are declared here
       Qout: out std_logic_vector (3 downto 0)); -- The output port is declared here
end e74194;

architecture Behavioral of e74194 is
signal Q: std_logic_vector (3 downto 0):= "0000"; -- internal storage declared here
begin
process (Q, S1, S0, clk, Clrn)
subtype slv2 is std_logic_vector(1 downto 0); -- subtype declared for using it in the case statement
begin
If Clrn = '0' then -- if clrn = 0 the internal storage should be cleared
   Q <= "0000";
elsif (clk'event and clk = '1') then -- during the positive edge of the clock signal the case statement will get executed
   case slv2'(S1 & S0) is -- Here checks the value of S1 and S0
   when "00" => null; -- when it is 00, the internal storage should hold the previous content
   when "01" => Q(3) <= RSIN; Q(2 downto 0) <= Q(3 downto 1); -- when it is 01, a right shift should occur
   when "10" => Q(0) <= LSIN; Q(3 downto 1) <= Q(2 downto 0); -- when it is 10, a left shift should occur
   when "11" => Q <= D; -- when it is 11, parallelly load a new data on to the internal storage
   when others => null; -- in all other cases, it should hold previous value
   end case; -- end of the case statement
end if; -- end of the if statement
Qout <= Q; -- assign output signal with internally stored value
end process; -- end of the process block

end Behavioral; -- end of the entity definition

The Screeshot of the code is given below for better readability.

library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.numeric_std.ALL; -- Entity Definition starts here entity e74194 is port (si, so, Clrn, RSIN, LSIN, clk : in std_logic; D: in std_logic_vector (3 downto 0); -- All th input ports are declared here Qout: out std_logic_vector (3 downto 0)); -- The output port is declared here end e74194; architecture Behavioral of e74194 is signal Q: std_logic_vector (3 downto 0):= "0000"; -- internal storage declared here begin process (Q, si, so, clk, Clrn) subtype slv2 is std_logic_vector(1 downto 0); -- subtype declared for using it in the case statement begin If Clrn = 'O' then -- if clrn = 0 the internal storage should be cleared Q <= "0000"; elsif (clk'event and clk = '1') then -- during the positive edge of the clock signal the case statement will get executed case slv2' (Sl & SO) is -- Here checks the value of sl and so when "00" => null; -- when it is 00, the internal storage should hold the previous content when "01" => 013) (= RSIN; 012 downto 0) <= 013 downto 1); -- when it is 01, a right shift should occur when "10" => 0(0) <= LSIN; 0(3 downto 1) <= Q(2 downto 0); -- when it is 10, a left shift should occur when "11" => 0 <= D; -- when it is li, parallelly load a new data on to the internal storage when others => null; -- in all other cases, it should hold previous value end case; -- end of the case statement end if; -- end of the if statement Qout <= 0; -- assign output signal end process; -- end of the process block end Behavioral; -- end of the entity definition

The simulation result of the VHDL code is given below.

/e/4194/s1 /e74194/50 /e74194/drn /e74194/rsin /e74194/sin /e74194/dk /e74194/d e74194/qout 1110 0110 10000 10110 1 110010000000 0001001101111011 1101_1110

please give me humb up