Question

Instructions: For all the questions you are required to submit VHDL codes & test bench simulation screenshot. If anything else is required it is mentioned in the question. Question 1.Design a 16 bit Increment Register with asynchronous reset, and increment capability using the following entity. Also, find out number of registers inferred by your code Entity reg16 is port ( clk, reset, inc load datain in stdalogic. in stdalogic. instdlogic vector (15 downto 0) out td.logicvector (15 downta 0); End reg16 Specifications: reset is active low and will asynchronously initialize the register to all zeros. Register will load a new value from data .iu when load ' on the next clock pulse When inc-'l', contents of the register will be incremented by one on the next clock pulse Load should have higher priority than inç Use positive edge clock for your design. Question 2 Design a circuit capable of ordering the bits of a vector, using sequential code. The ordering should be from left to right, with all '1's coming first (e.g ""0001 1001" would become "1110_0000"). Vector should be of generic length. Binarv sorter

Please answer both questions

Answer 1

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity reg16 is
   port (   clk, reset, inc   : in std_logic;
       load       : in std_logic;
       data_in       : in std_logic_vector (15 downto 0);
       q       : out std_logic_vector (15 downto 0)
   );
end reg16;

architecture arch of reg16 is

signal qreg : std_logic_vector (15 downto 0);

begin

process (clk, reset)

begin

   if (reset = '0') then

       qreg <= X"0000";

   else

       if rising_edge(clk) then

           if (load = '1') then

               qreg <= data_in;

            else

               if (inc = '1') then

                   qreg <= qreg + '1';

               end if;

           end if;

       end if;

   end if;

   q <= qreg;

end process;

end arch;

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Wave File Edit View Add Format Tools Bookmarks Window Help Wave -Default Msgs freg16/ck freg 16freset reg 16 nc reg 16/oed freg 16/data-in uuuiwwu 1100110100000010 ICCc 110011010000001 1400 ps 400 1400 0 ps to 1470 ps Now: 1,400 ps Dela: 2 11:14 PM O Type here to search x® 、彫后20冫3/24/2019

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library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity vector is
   generic (length : natural := 8);
   port (   data_in       : in std_logic_vector (length downto 1);
       dout       : out std_logic_vector (length downto 1)
   );
end vector;

architecture arch of vector is

begin

process (data_in)

variable reg : std_logic_vector (length downto 1);

begin
   reg := (others=>'0');

   for i in 1 to length loop

       if (data_in(i) = '1') then

           reg := '1' & reg(length downto 2);
       end if;

   end loop;

dout <= reg;
      
end process;

end arch;

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Wave 0 File Edit View Add Format Tools Bookmarks Window Help Wave -Default Msgs vector fdata _in 00000001 400 0 ps to 420 ps Now: 400 ps Delta: 0 1229 AM O Type here to search