Question

Assignment:

Implement an 8 bit register in VHDL/Verilog using Model Sim software. Show two test cases for data read and write into the register.

The register has an enable and reset signal. When the reset is high the register should be cleared. When the enable is high and reset is low, data should be written into the register.

Hint: The demo code shown below has the implementation for a 4-bit register that can be used as an example.

library ieee;

use ieee.std_logic_1164.all;

entity reg_4bit is

port (reset,enable:in bit;

clock:inout bit;

i:in bit_vector(3 downto 0);

q:out bit_vector(3 downto 0));

end entity reg_4bit;

architecture behav of reg_4bit is

begin

p1:process(clock,i,reset,enable)

begin

if (reset='1') then

q<="0000";

end if;

if (clock='1') and (reset='0') and (enable='1') then

q<=i;

end if;

end process p1;

end architecture behav;

Answer 1

file dff.v

module dff(
       input clk,reset,enable,d,
       output reg Q
);
always@(posedge clk)
begin
           if(reset)
           Q <=0;
       else if(enable)
           Q <=d;
   end

endmodule

file 8_bit_reg,v

module register(
   input [7:0] in,
   input clk,
   output [7:0] out
  
);

dff u[7:0](clk,0,1,in,out);

endmodule