library ieee;
use ieee.std_logic_1164.all;
entity SR4P is
port ( InBit, Clock, L : in
std_logic;
R :
in std_logic_vector(3 downto 0);
OutVec
: out std_logic_vector(3 downto 0)
);
end SR4P;
architecture behavorial of SR4P is
signal Q : std_logic_vector(3 downto 0) := "0000";
begin
process (Clock)
begin
if rising_edge(Clock) then
if L = '1' then
Q <= R;
else
Q(3) <=
InBit;
Q(2) <=
Q(3);
Q(1) <=
Q(2);
Q(0) <=
Q(1);
end if;
end if;
end process;
OutVec <= Q;
end behavorial;
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