Homework Answers
1) Hardware description language
2)blocks
3) end
4) entity
5) architecture
6) true
7) strongly typed language
8) bit
9) b and c
10) to be portable
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Some questions may require well bulum 1. HDL stands for? a. Hardware Design Language b. Hardware...
QUESTION 1 Complete the following peice of VHDL code with the necessary VHDL statements for a...
QUESTION 1 Complete the following peice of VHDL code with the necessary VHDL statements for a counter that counts through this sequence(0,9,17,15,4,26) repeatedly. library IEEE use IEEE.STD_LOGIC_1164 ALL entity GCC is Port ( systemClock, reset in STD_LOGIC end GCC architecture Behavioral of GCC is stateOutput out STD LOGIC_ VECTOR (4 downto 0)) component FreqDivider is Port (systemClock in STD_LOGIC; slowClock: out STD LOGIC); end component, signal nextState, presentState: std_logic_vector(5 downto 0) := "00000"; signal slowClock: std_logic begin FD0: FreqDivider port...
8.(5 points).There is an error in following VHDL code. Find the error and correct (only that...
8.(5 points).There is an error in following VHDL code. Find the error and correct (only that line of code). LIBRARY ieee; USE ieee.std_logic_1164.all; ENTITY dec2to4 IS PORT (i IN STD LOGIC VECTOR (1 DOWNTO 0); : En IN STD_LOGIC; d OUT STD LOGIC); END dec2to4; ARCHITECTURE dataflow OF dec2to4 IS BEGIN SIGNAL Eni: STD_LOGIC_VECTOR(2 DOWNTO 0); Eni <= En & i; -concatenate signals WITH Eni SELECT d <"0001" WHEN "100" "0010" WHEN "101", "0100" WHEN "110", "1000" WHEN "111", 0000"...
b. Suppose you are provided with a 4-bit ripple carry adder. It has the following entity...
b. Suppose you are provided with a 4-bit ripple carry adder. It has the following entity declaration and schematic representation А(3:0] B[3: entity fourbit FA is portA, B in std logic_vector (3 downto 0); 4-bit RCA Cin in std_logic; S out stdlogic_vector (3 downto 0) Cout out std logic: Cin Cout S3:0] end fourbitFA Create a VHDL architecture for the following circuit (15 Marks) C3:0] D[3:0] A[3:0] B[3:0] Е[3:0] F[3:0] 4-bit RCA 4-bit RCA inA 4-bit RCA CinB CinC Coutl...
S2) Draw the logic circuit on the side of which the given VHDL code is real....
S2) Draw the logic circuit on the side of which the given VHDL code is real. library IEEE; use IEEE.STD_LOGIC_1164.ALL; entity devre is 81: out STD_LOGIC; Y2 : out port (A,B,C : in STD_LOGIC; STD_LOGIC); end devre; architecture behavioral of devre is begin Y1 <= (A xor B) and (not C); Y2 <= (A and (B or C)); end behavioral;
Name: ·5. (10 lts) Find and correct errors in the following VHDL ed. IEEE ; library use IEEE . STD LOGIC-1104 . all...
Name: ·5. (10 lts) Find and correct errors in the following VHDL ed. IEEE ; library use IEEE . STD LOGIC-1104 . all; entity cicuitl is port (a, b, elk: in STD_LOGIC: This part of the code its correct.That is, the entity definition and the 1ibraries are written correctly S out STD LOGIC) ond; architecture synth of eicuiti is begin This part of the code ธhould be a process that groups input a and input b together to forn a...
Draw the RTL schematic of the hardware that will be synthesized for the VHDL code below....
Draw the RTL schematic of the hardware that will be synthesized for the VHDL code below. entity unknown is port (x: in std_logic_vector(7 downto 0); op: in std_logic_vector(1 downto 0); clk: in std_logic; f: out std_logic_vector(7 downto 0)); end entity. architecture arch of unknown is signal a, b, c, d: std_logic_vector(7 downto 0); begin d <= x; process (clk) begin if (rising_edge(clk)) then a <= b; b <= c + a; c <= d; if (op = “00”) then f...
If the delay of or-gate is 10ns, the flip-flop is 6ns, and the gate-to-gate delay is 4ns Calculate the frequency of the...
If the delay of or-gate is 10ns, the flip-flop is 6ns, and the gate-to-gate delay is 4ns Calculate the frequency of the following two functionally identical circuits. Which one is faster? Explain why entity foo is port (a, b, c, d: in STD_LOGIC; x: out STD_LOGIC) end foo architecture verl of foo is signal templ, temp2: STD LOGIC; begin temp1< a or b; temp2 <= templ or c; x <= temp2 or d; end architecture verl; entity foo is port...
SRAP pr- Vivado 2017. Eile Edit Flow Iools Window Layout Yew HelpQuick Acces Ready VO Planning Fl...
SRAP pr- Vivado 2017. Eile Edit Flow Iools Window Layout Yew HelpQuick Acces Ready VO Planning Flow Navigator V PROJECT MANAGER Cell Properties x Clock Regions ?-OC Package x Device xsrapvhd × Schematic X O Setings Language Templates IP Catalog IPINTEGRATOR Open Block Design Qngl3이 OutVed3이 Generate Block Design SIMULATION R3.0 Run Simulation RTL ANALYSIS n Elaborated Design 白Report Methodology Report DRC Report Noise Schematic Td Console Messages Lg Reports Design Runs Package Pins VO Ports Type here to search...
Please fully answer BOTH parts of the question (a) and (b). a) Draw the high level...
Please fully answer BOTH parts of the question (a) and (b). a) Draw the high level synthesized diagram of the following VHDL code. What does the following circuit do? Write the sequence of output generated by this circuit. library ieee; use ieee.std_logic_1164.all; entity sequence is port ( cout :out std_logic_vector (3 downto 0); clk :in std_logic; reset :in std_logic ); end entity; architecture rtl of sequence is signal count :std_logic_vector (3 downto 0); begin process (clk) begin if (rising_edge(clk)) then...
A Y = A+ B 1 1 1 1 1 1 Apply the idea of the truth table above and design a 3-bit comparator using XOR or XNOR gates of...
A Y = A+ B 1 1 1 1 1 1 Apply the idea of the truth table above and design a 3-bit comparator using XOR or XNOR gates of your choice. The design should be able to determine the equality between two 3-bit words. An LED should be turned ON only when every bit in "Word A" matches every corresponding bit in "Word B". Otherwise, the LED has to be OFF Hint for I/O port Definitions: Port Name MSB...
QUESTION 1 Complete the following peice of VHDL code with the necessary VHDL statements for a counter that counts through this sequence(0,9,17,15,4,26) repeatedly. library IEEE use IEEE.STD_LOGIC_1164 ALL entity GCC is Port ( systemClock, reset in STD_LOGIC end GCC architecture Behavioral of GCC is stateOutput out STD LOGIC_ VECTOR (4 downto 0)) component FreqDivider is Port (systemClock in STD_LOGIC; slowClock: out STD LOGIC); end component, signal nextState, presentState: std_logic_vector(5 downto 0) := "00000"; signal slowClock: std_logic begin FD0: FreqDivider port...
8.(5 points).There is an error in following VHDL code. Find the error and correct (only that line of code). LIBRARY ieee; USE ieee.std_logic_1164.all; ENTITY dec2to4 IS PORT (i IN STD LOGIC VECTOR (1 DOWNTO 0); : En IN STD_LOGIC; d OUT STD LOGIC); END dec2to4; ARCHITECTURE dataflow OF dec2to4 IS BEGIN SIGNAL Eni: STD_LOGIC_VECTOR(2 DOWNTO 0); Eni <= En & i; -concatenate signals WITH Eni SELECT d <"0001" WHEN "100" "0010" WHEN "101", "0100" WHEN "110", "1000" WHEN "111", 0000"...
b. Suppose you are provided with a 4-bit ripple carry adder. It has the following entity declaration and schematic representation А(3:0] B[3: entity fourbit FA is portA, B in std logic_vector (3 downto 0); 4-bit RCA Cin in std_logic; S out stdlogic_vector (3 downto 0) Cout out std logic: Cin Cout S3:0] end fourbitFA Create a VHDL architecture for the following circuit (15 Marks) C3:0] D[3:0] A[3:0] B[3:0] Е[3:0] F[3:0] 4-bit RCA 4-bit RCA inA 4-bit RCA CinB CinC Coutl...
S2) Draw the logic circuit on the side of which the given VHDL code is real. library IEEE; use IEEE.STD_LOGIC_1164.ALL; entity devre is 81: out STD_LOGIC; Y2 : out port (A,B,C : in STD_LOGIC; STD_LOGIC); end devre; architecture behavioral of devre is begin Y1 <= (A xor B) and (not C); Y2 <= (A and (B or C)); end behavioral;
Name: ·5. (10 lts) Find and correct errors in the following VHDL ed. IEEE ; library use IEEE . STD LOGIC-1104 . all; entity cicuitl is port (a, b, elk: in STD_LOGIC: This part of the code its correct.That is, the entity definition and the 1ibraries are written correctly S out STD LOGIC) ond; architecture synth of eicuiti is begin This part of the code ธhould be a process that groups input a and input b together to forn a...
If the delay of or-gate is 10ns, the flip-flop is 6ns, and the gate-to-gate delay is 4ns Calculate the frequency of the following two functionally identical circuits. Which one is faster? Explain why entity foo is port (a, b, c, d: in STD_LOGIC; x: out STD_LOGIC) end foo architecture verl of foo is signal templ, temp2: STD LOGIC; begin temp1< a or b; temp2 <= templ or c; x <= temp2 or d; end architecture verl; entity foo is port...
SRAP pr- Vivado 2017. Eile Edit Flow Iools Window Layout Yew HelpQuick Acces Ready VO Planning Flow Navigator V PROJECT MANAGER Cell Properties x Clock Regions ?-OC Package x Device xsrapvhd × Schematic X O Setings Language Templates IP Catalog IPINTEGRATOR Open Block Design Qngl3이 OutVed3이 Generate Block Design SIMULATION R3.0 Run Simulation RTL ANALYSIS n Elaborated Design 白Report Methodology Report DRC Report Noise Schematic Td Console Messages Lg Reports Design Runs Package Pins VO Ports Type here to search...
A Y = A+ B 1 1 1 1 1 1 Apply the idea of the truth table above and design a 3-bit comparator using XOR or XNOR gates of your choice. The design should be able to determine the equality between two 3-bit words. An LED should be turned ON only when every bit in "Word A" matches every corresponding bit in "Word B". Otherwise, the LED has to be OFF Hint for I/O port Definitions: Port Name MSB...
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