Homework Answers
with in entity block, in the port declaration, output "d" is declared as one bit variable but not as vector. But it should be vector .
d : OUT STD_LOGIC_VECTOR(3 downto 0); --------is the correct statement ....
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8.(5 points).There is an error in following VHDL code. Find the error and correct (only that...
QUESTION 1 Complete the following peice of VHDL code with the necessary VHDL statements for a...
QUESTION 1 Complete the following peice of VHDL code with the necessary VHDL statements for a counter that counts through this sequence(0,9,17,15,4,26) repeatedly. library IEEE use IEEE.STD_LOGIC_1164 ALL entity GCC is Port ( systemClock, reset in STD_LOGIC end GCC architecture Behavioral of GCC is stateOutput out STD LOGIC_ VECTOR (4 downto 0)) component FreqDivider is Port (systemClock in STD_LOGIC; slowClock: out STD LOGIC); end component, signal nextState, presentState: std_logic_vector(5 downto 0) := "00000"; signal slowClock: std_logic begin FD0: FreqDivider port...
3. Study the VHDL code below for the multiplexer: -mux.vhd library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all;...
3. Study the VHDL code below for the multiplexer: -mux.vhd library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; use jeee.std logic.arith.all; entity mux is port DIFF1, DIFF2: n std_logic_vector(4 downto O); ABSLT: out std_logic_vector(4 downto 0); CO: in std logic ); end mux; architecture behv of mux is begin with CO select ABSLT DIFF1 when o, a CO-0 selects B-A DIFF2 when 1',a Co-1 selects A-B "ZZZZZ" when others·.. high impedance otherwise end behy
Write a test bench for the following VHDL code -------------------------------------------------------------------------------------------------------------------------------- LIBRARY ieee ; USE ieee.std_logic_1164.all ;...
Write a test bench for the following VHDL code -------------------------------------------------------------------------------------------------------------------------------- LIBRARY ieee ; USE ieee.std_logic_1164.all ; ENTITY registern IS GENERIC (N: INTEGER :=4); -- INTEGER=32, 16, ….. PORT (D : IN STD_LOGIC_VECTOR (N-1 downto 0); clk, reset, Load : IN STD_LOGIC ; Q : OUT STD_LOGIC_VECTOR (N-1 downto 0 )) ; END registern; ARCHITECTURE behavior OF registern IS BEGIN PROCESS (clk) BEGIN IF clk' EVENT AND clk='1' THEN IF (reset ='0') THEN --synchronous reset Q<=(OTHERS=>’0’); ELSIF (L ='0') THEN Q<=D;...
S2) Draw the logic circuit on the side of which the given VHDL code is real....
S2) Draw the logic circuit on the side of which the given VHDL code is real. library IEEE; use IEEE.STD_LOGIC_1164.ALL; entity devre is 81: out STD_LOGIC; Y2 : out port (A,B,C : in STD_LOGIC; STD_LOGIC); end devre; architecture behavioral of devre is begin Y1 <= (A xor B) and (not C); Y2 <= (A and (B or C)); end behavioral;
Name: ·5. (10 lts) Find and correct errors in the following VHDL ed. IEEE ; library use IEEE . STD LOGIC-1104 . all...
Name: ·5. (10 lts) Find and correct errors in the following VHDL ed. IEEE ; library use IEEE . STD LOGIC-1104 . all; entity cicuitl is port (a, b, elk: in STD_LOGIC: This part of the code its correct.That is, the entity definition and the 1ibraries are written correctly S out STD LOGIC) ond; architecture synth of eicuiti is begin This part of the code ธhould be a process that groups input a and input b together to forn a...
Problem 5 (8 pts) Write a VHDL code (including an entity definition and an architecture definition)...
Problem 5 (8 pts) Write a VHDL code (including an entity definition and an architecture definition) to describe a 8:1 multiplexer in which each input port is of type STD_LOGIC_VECTOR and each input port has 4 bits, and the output Y is also a STD_LOGIC_VECTOR with 4 bits. Your code's architecture definition should use "with...select..." structure. The code to include header files is already given below. library IEEE; use IEEE.STD_LOGIC_1164.all;
Question 18 (5 points) LIBRARY ece USE ieee.std logic 1164.all ENTITY prob6 21 IS PORT (w...
Question 18 (5 points) LIBRARY ece USE ieee.std logic 1164.all ENTITY prob6 21 IS PORT (w IN STD LOGIC VECTOR(3 DOWNTO 0) y: OUT STD LOGIC VECTOR(I DOWNTO 0)); END prob6 21 ARCHITECTURE Behavior OF prob6 21 IS BEGIN WITH w SELECT y <= "O0" WHEN "0001" ..01.. WHEN "O010", "10" WHEN 0100" 11" WHEN OTHERS END Behavior What type of circuit does the VHDL code represents? 4-bit shifter a 4-to-2 binary encoder A two bit multiplier None of the...
Please fully answer BOTH parts of the question (a) and (b). a) Draw the high level...
Please fully answer BOTH parts of the question (a) and (b). a) Draw the high level synthesized diagram of the following VHDL code. What does the following circuit do? Write the sequence of output generated by this circuit. library ieee; use ieee.std_logic_1164.all; entity sequence is port ( cout :out std_logic_vector (3 downto 0); clk :in std_logic; reset :in std_logic ); end entity; architecture rtl of sequence is signal count :std_logic_vector (3 downto 0); begin process (clk) begin if (rising_edge(clk)) then...
Write a VHDL code using processes for the following logic circuit which include a shift register...
Write a VHDL code using processes for the following logic
circuit which include a shift register and 4x1 multiplexer. Use the
entity below.
entity registers_min_max is
port( din : in std_logic_vector(3 downto 0);
reset : in std_logic;
clk : in
std_logic;
sel : in
std_logic_vector(1 downto 0);
reg_out : out std_logic_vector(3
downto 0));
end registers_min_max;
din reset RO clk reset R1 A C clk reset R2 clk reset R3 clk 3 0 sel LE
Draw the RTL schematic of the hardware that will be synthesized for the VHDL code below....
Draw the RTL schematic of the hardware that will be synthesized for the VHDL code below. entity unknown is port (x: in std_logic_vector(7 downto 0); op: in std_logic_vector(1 downto 0); clk: in std_logic; f: out std_logic_vector(7 downto 0)); end entity. architecture arch of unknown is signal a, b, c, d: std_logic_vector(7 downto 0); begin d <= x; process (clk) begin if (rising_edge(clk)) then a <= b; b <= c + a; c <= d; if (op = “00”) then f...
QUESTION 1 Complete the following peice of VHDL code with the necessary VHDL statements for a counter that counts through this sequence(0,9,17,15,4,26) repeatedly. library IEEE use IEEE.STD_LOGIC_1164 ALL entity GCC is Port ( systemClock, reset in STD_LOGIC end GCC architecture Behavioral of GCC is stateOutput out STD LOGIC_ VECTOR (4 downto 0)) component FreqDivider is Port (systemClock in STD_LOGIC; slowClock: out STD LOGIC); end component, signal nextState, presentState: std_logic_vector(5 downto 0) := "00000"; signal slowClock: std_logic begin FD0: FreqDivider port...
3. Study the VHDL code below for the multiplexer: -mux.vhd library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; use jeee.std logic.arith.all; entity mux is port DIFF1, DIFF2: n std_logic_vector(4 downto O); ABSLT: out std_logic_vector(4 downto 0); CO: in std logic ); end mux; architecture behv of mux is begin with CO select ABSLT DIFF1 when o, a CO-0 selects B-A DIFF2 when 1',a Co-1 selects A-B "ZZZZZ" when others·.. high impedance otherwise end behy
S2) Draw the logic circuit on the side of which the given VHDL code is real. library IEEE; use IEEE.STD_LOGIC_1164.ALL; entity devre is 81: out STD_LOGIC; Y2 : out port (A,B,C : in STD_LOGIC; STD_LOGIC); end devre; architecture behavioral of devre is begin Y1 <= (A xor B) and (not C); Y2 <= (A and (B or C)); end behavioral;
Name: ·5. (10 lts) Find and correct errors in the following VHDL ed. IEEE ; library use IEEE . STD LOGIC-1104 . all; entity cicuitl is port (a, b, elk: in STD_LOGIC: This part of the code its correct.That is, the entity definition and the 1ibraries are written correctly S out STD LOGIC) ond; architecture synth of eicuiti is begin This part of the code ธhould be a process that groups input a and input b together to forn a...
Problem 5 (8 pts) Write a VHDL code (including an entity definition and an architecture definition) to describe a 8:1 multiplexer in which each input port is of type STD_LOGIC_VECTOR and each input port has 4 bits, and the output Y is also a STD_LOGIC_VECTOR with 4 bits. Your code's architecture definition should use "with...select..." structure. The code to include header files is already given below. library IEEE; use IEEE.STD_LOGIC_1164.all;
Question 18 (5 points) LIBRARY ece USE ieee.std logic 1164.all ENTITY prob6 21 IS PORT (w IN STD LOGIC VECTOR(3 DOWNTO 0) y: OUT STD LOGIC VECTOR(I DOWNTO 0)); END prob6 21 ARCHITECTURE Behavior OF prob6 21 IS BEGIN WITH w SELECT y <= "O0" WHEN "0001" ..01.. WHEN "O010", "10" WHEN 0100" 11" WHEN OTHERS END Behavior What type of circuit does the VHDL code represents? 4-bit shifter a 4-to-2 binary encoder A two bit multiplier None of the...
Write a VHDL code using processes for the following logic
circuit which include a shift register and 4x1 multiplexer. Use the
entity below.
entity registers_min_max is
port( din : in std_logic_vector(3 downto 0);
reset : in std_logic;
clk : in
std_logic;
sel : in
std_logic_vector(1 downto 0);
reg_out : out std_logic_vector(3
downto 0));
end registers_min_max;
din reset RO clk reset R1 A C clk reset R2 clk reset R3 clk 3 0 sel LE
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