Homework Answers
Logic diagram:
* created using creately website
For output Y1:
1) XOR A, B
2) NOT B
3) AND outputs of 1) and 2)
For Output Y2:
1) OR B., C
2) AND A, output of 1)
Add Answer to:
S2) Draw the logic circuit on the side of which the given VHDL code is real....
QUESTION 1 Complete the following peice of VHDL code with the necessary VHDL statements for a...
QUESTION 1 Complete the following peice of VHDL code with the necessary VHDL statements for a counter that counts through this sequence(0,9,17,15,4,26) repeatedly. library IEEE use IEEE.STD_LOGIC_1164 ALL entity GCC is Port ( systemClock, reset in STD_LOGIC end GCC architecture Behavioral of GCC is stateOutput out STD LOGIC_ VECTOR (4 downto 0)) component FreqDivider is Port (systemClock in STD_LOGIC; slowClock: out STD LOGIC); end component, signal nextState, presentState: std_logic_vector(5 downto 0) := "00000"; signal slowClock: std_logic begin FD0: FreqDivider port...
8.(5 points).There is an error in following VHDL code. Find the error and correct (only that...
8.(5 points).There is an error in following VHDL code. Find the error and correct (only that line of code). LIBRARY ieee; USE ieee.std_logic_1164.all; ENTITY dec2to4 IS PORT (i IN STD LOGIC VECTOR (1 DOWNTO 0); : En IN STD_LOGIC; d OUT STD LOGIC); END dec2to4; ARCHITECTURE dataflow OF dec2to4 IS BEGIN SIGNAL Eni: STD_LOGIC_VECTOR(2 DOWNTO 0); Eni <= En & i; -concatenate signals WITH Eni SELECT d <"0001" WHEN "100" "0010" WHEN "101", "0100" WHEN "110", "1000" WHEN "111", 0000"...
draw a block diagram of the circuit represented by the vhdl code listed below. be sure...
draw a block diagram of the circuit represented by the vhdl
code listed below. be sure to completely label the final
diagram
Draw a block diagram of the circuit represented by the VHDL code listed below. Be sure to completely label the final diagram. -- library declaration library IEEE; use IEEE.std logic 1164.all; -- entity entity ckti is Port (EN, EN2 : in std logic; CLK : in std logic; Z! out std logie); end ckt1; -- architecture architecture arch...
Given the following VHDL code, write the simplified Boolean equations for the outputs and sketch the...
Given the following VHDL code, write the simplified Boolean equations for the outputs and sketch the circuit schematic. entity newFunction is /*entity declaration*/ port(a, b, c: in STD_LOGIC; y: out STD_LOGIC); Z: out STD_LOGIC); end; architecture synth of newFunction is /*architecture body*/ begin y <= (not a and b and not c) or (a and b and not c) z <= (a and b and c) or (not a and b and not c) or...
Write a test bench for the following VHDL code -------------------------------------------------------------------------------------------------------------------------------- LIBRARY ieee ; USE ieee.std_logic_1164.all ;...
Write a test bench for the following VHDL code -------------------------------------------------------------------------------------------------------------------------------- LIBRARY ieee ; USE ieee.std_logic_1164.all ; ENTITY registern IS GENERIC (N: INTEGER :=4); -- INTEGER=32, 16, ….. PORT (D : IN STD_LOGIC_VECTOR (N-1 downto 0); clk, reset, Load : IN STD_LOGIC ; Q : OUT STD_LOGIC_VECTOR (N-1 downto 0 )) ; END registern; ARCHITECTURE behavior OF registern IS BEGIN PROCESS (clk) BEGIN IF clk' EVENT AND clk='1' THEN IF (reset ='0') THEN --synchronous reset Q<=(OTHERS=>’0’); ELSIF (L ='0') THEN Q<=D;...
PROBLEM 3 (16 PTS) ▪ With a D flip flop and logic gates, sketch the circuit...
PROBLEM 3 (16 PTS) ▪ With a D
flip flop and logic gates, sketch the circuit whose excitation
equation is given by:
PROBLEM 3 (16 PTS) • With a D flip flop and logic gates, sketch the circuit whose excitation equation is given by: Qit+1) + y + Q(t) + y(t) (4 pts) • Complete the timing diagram of the circuit whose VHDL description is shown below. Also, get the excitation equation for q. library ieee: elsaf (cll'event and clk...
Identify and correct the mistakes of code. Identify and draw table for the circuit. library ieee;...
Identify and correct the mistakes of code.
Identify and draw table for the circuit.
library ieee; 1 use ieee.std_logic_1164.all; 2 3 entity mux4x1_seq is 4. 5 port 6 ip0: ip1: ip2: ip3 in std_logic; 7 in std_logic_vector(0 to 1); out std_logic}; 9 op end mux4x1_seq}; 10 11 architecture beh of mux4x1_seq is 12 13 |begin 14 P_mux: process (ip0,ip1,ip2,ip3,s); variable temp: std_logic; 15 16 begin 17 case s is 18 temp ip0; when "00" => 19 when "01" temp ip1;...
3. Study the VHDL code below for the multiplexer: -mux.vhd library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all;...
3. Study the VHDL code below for the multiplexer: -mux.vhd library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; use jeee.std logic.arith.all; entity mux is port DIFF1, DIFF2: n std_logic_vector(4 downto O); ABSLT: out std_logic_vector(4 downto 0); CO: in std logic ); end mux; architecture behv of mux is begin with CO select ABSLT DIFF1 when o, a CO-0 selects B-A DIFF2 when 1',a Co-1 selects A-B "ZZZZZ" when others·.. high impedance otherwise end behy
Please fully answer BOTH parts of the question (a) and (b). a) Draw the high level...
Please fully answer BOTH parts of the question (a) and (b). a) Draw the high level synthesized diagram of the following VHDL code. What does the following circuit do? Write the sequence of output generated by this circuit. library ieee; use ieee.std_logic_1164.all; entity sequence is port ( cout :out std_logic_vector (3 downto 0); clk :in std_logic; reset :in std_logic ); end entity; architecture rtl of sequence is signal count :std_logic_vector (3 downto 0); begin process (clk) begin if (rising_edge(clk)) then...
Some questions may require well bulum 1. HDL stands for? a. Hardware Design Language b. Hardware...
Some questions may require well bulum 1. HDL stands for? a. Hardware Design Language b. Hardware Development Language c. Hardware Description language d. Hot Dry Land 2. What is the basic building unit of a VHDL design? a. Blocks b. Cubes c . Dices d. Bricks 3. What reserved word do all VHDL entities end with? a. entity b. use c. port d. end d. IEEE 4. Which block describes a design's interface? a. entity b. architecture c. library 5....
QUESTION 1 Complete the following peice of VHDL code with the necessary VHDL statements for a counter that counts through this sequence(0,9,17,15,4,26) repeatedly. library IEEE use IEEE.STD_LOGIC_1164 ALL entity GCC is Port ( systemClock, reset in STD_LOGIC end GCC architecture Behavioral of GCC is stateOutput out STD LOGIC_ VECTOR (4 downto 0)) component FreqDivider is Port (systemClock in STD_LOGIC; slowClock: out STD LOGIC); end component, signal nextState, presentState: std_logic_vector(5 downto 0) := "00000"; signal slowClock: std_logic begin FD0: FreqDivider port...
8.(5 points).There is an error in following VHDL code. Find the error and correct (only that line of code). LIBRARY ieee; USE ieee.std_logic_1164.all; ENTITY dec2to4 IS PORT (i IN STD LOGIC VECTOR (1 DOWNTO 0); : En IN STD_LOGIC; d OUT STD LOGIC); END dec2to4; ARCHITECTURE dataflow OF dec2to4 IS BEGIN SIGNAL Eni: STD_LOGIC_VECTOR(2 DOWNTO 0); Eni <= En & i; -concatenate signals WITH Eni SELECT d <"0001" WHEN "100" "0010" WHEN "101", "0100" WHEN "110", "1000" WHEN "111", 0000"...
draw a block diagram of the circuit represented by the vhdl
code listed below. be sure to completely label the final
diagram
Draw a block diagram of the circuit represented by the VHDL code listed below. Be sure to completely label the final diagram. -- library declaration library IEEE; use IEEE.std logic 1164.all; -- entity entity ckti is Port (EN, EN2 : in std logic; CLK : in std logic; Z! out std logie); end ckt1; -- architecture architecture arch...
PROBLEM 3 (16 PTS) ▪ With a D
flip flop and logic gates, sketch the circuit whose excitation
equation is given by:
PROBLEM 3 (16 PTS) • With a D flip flop and logic gates, sketch the circuit whose excitation equation is given by: Qit+1) + y + Q(t) + y(t) (4 pts) • Complete the timing diagram of the circuit whose VHDL description is shown below. Also, get the excitation equation for q. library ieee: elsaf (cll'event and clk...
Identify and correct the mistakes of code.
Identify and draw table for the circuit.
library ieee; 1 use ieee.std_logic_1164.all; 2 3 entity mux4x1_seq is 4. 5 port 6 ip0: ip1: ip2: ip3 in std_logic; 7 in std_logic_vector(0 to 1); out std_logic}; 9 op end mux4x1_seq}; 10 11 architecture beh of mux4x1_seq is 12 13 |begin 14 P_mux: process (ip0,ip1,ip2,ip3,s); variable temp: std_logic; 15 16 begin 17 case s is 18 temp ip0; when "00" => 19 when "01" temp ip1;...
3. Study the VHDL code below for the multiplexer: -mux.vhd library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; use jeee.std logic.arith.all; entity mux is port DIFF1, DIFF2: n std_logic_vector(4 downto O); ABSLT: out std_logic_vector(4 downto 0); CO: in std logic ); end mux; architecture behv of mux is begin with CO select ABSLT DIFF1 when o, a CO-0 selects B-A DIFF2 when 1',a Co-1 selects A-B "ZZZZZ" when others·.. high impedance otherwise end behy
Some questions may require well bulum 1. HDL stands for? a. Hardware Design Language b. Hardware Development Language c. Hardware Description language d. Hot Dry Land 2. What is the basic building unit of a VHDL design? a. Blocks b. Cubes c . Dices d. Bricks 3. What reserved word do all VHDL entities end with? a. entity b. use c. port d. end d. IEEE 4. Which block describes a design's interface? a. entity b. architecture c. library 5....
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