Question

Write a test bench for the following VHDL code

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LIBRARY ieee ;

USE ieee.std_logic_1164.all ;

ENTITY registern IS

GENERIC (N: INTEGER :=4);    -- INTEGER=32, 16, …..

PORT (D           : IN STD_LOGIC_VECTOR (N-1 downto 0);

clk, reset, Load   : IN      STD_LOGIC ;

Q           : OUT   STD_LOGIC_VECTOR (N-1 downto 0 )) ;

END registern;

ARCHITECTURE behavior OF registern IS

BEGIN

PROCESS (clk)

BEGIN

IF clk' EVENT AND clk='1' THEN

IF (reset ='0') THEN    --synchronous reset

Q<=(OTHERS=>’0’);

ELSIF (L ='0') THEN Q<=D;

END IF;

END IF;

END PROCESS;

end Behavior;

Answer 1

TESTBENCH CODE:-

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity tb1 is
-- Port ( );
end tb1;

architecture Behavioral of tb1 is
component registern IS

GENERIC (N: INTEGER :=4);

PORT (D : IN STD_LOGIC_VECTOR (N-1 downto 0);

clk, reset, Load: IN STD_LOGIC ;

Q : OUT STD_LOGIC_VECTOR (N-1 downto 0 )) ;

END component;
signal td,tq:std_logic_vector(3 downto 0);
signal tload:std_logic;
signal tclk: std_logic := '0';
signal treset: std_logic := '0';
begin
treset<='0' , '1' after 10 ns;
tload<='0' , '1'after 15 ns, '0' after 25 ns , '1' after 40 ns , '0' after 50 ns , '1' after 60 ns, '0' after 70 ns , '1' after 80 ns;
td<="0001" , "1011" after 12ns , "0101" after 25 ns , "0011" after 35 ns , "1001" after 50 ns , "1111" after 70 ns;
Uut: registern
generic map(N=>4)
PORT MAP(td,tclk,treset,tload,tq);
process
begin
wait for 5ns;
tclk<=not tclk;
end process;
end Behavioral;

WAVEFORM:-

Name Value 40 ns ,60 ns 80 ns ,100 ns 120 ns 140 ns ,160 ns ,180 ns > > Y 3Y9 td[3:0] tq[3:0] 18 tload 16 telk 16 treset Activate Window