Draw the RTL schematic of the hardware that will be synthesized for the VHDL code below....
Draw the RTL schematic of the hardware that will be synthesized for the VHDL code below.
entity unknown is
port (x: in std_logic_vector(7 downto 0);
op: in std_logic_vector(1 downto 0);
clk: in std_logic;
f: out std_logic_vector(7 downto 0));
end entity.
architecture arch of unknown is
signal a, b, c, d: std_logic_vector(7 downto 0);
begin
d <= x;
process (clk)
begin
if (rising_edge(clk)) then
a <= b;
b <= c + a;
c <= d;
if (op = “00”) then
f <= a;
elsif (op =”01”) then
f <= a + b;
elsif (op=”10”) then
f <= b + c;
else
f <= d + c;
end if;
end process;
end architecture;
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Draw the RTL schematic of the hardware that will be synthesized
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