Question

Write a VHDL code using processes for the following logic circuit which include a shift register and 4x1 multiplexer. Use the entity below.             

entity registers_min_max is
port( din   : in std_logic_vector(3 downto 0);
      reset : in std_logic;
      clk   : in std_logic;
      sel   : in std_logic_vector(1 downto 0);
      reg_out : out std_logic_vector(3 downto 0));
end registers_min_max;

din reset RO clk reset R1 A C clk reset R2 clk reset R3 clk 3 0 sel LE

0 0
Add a comment Improve this question Transcribed image text
Answer #1

library ieee;
use ieee.std_logic_1164.all;


entity registers_min_max is
port( din : in std_logic; -- the din port is only single bit as in figure
reset : in std_logic;
clk : in std_logic;
sel : in std_logic_vector(1 downto 0);
LE : out std_logic; -- as LE is taken from the output of the mux as in figure//
out : out std_logic_vector(3 downto 0));
end registers_min_max;

architecture behave of register_min_max is
begin

shift1 : shift_register (clk => clk, reset => reset, din => din, out => temp );
mux : mux4x1 (in1 => temp, sel => sel, Y => LE);

out <= temp;

end behave;


library ieee;
use ieee.std_logic_1164.all;

entity shift_register is
port (
clk : in std_logic;
reset : in std_logic;
din : in std_logic;
out1 : out std_logic_vector(3 downto 0)
);
end shift_register;

architecture behave of shift_register is
signal temp : std_logic_vector (3 downto 0);
begin
U1:process (clk)
begin
if (clk'event and clk = '1') then
if (reset = '1') then
temp <= "0000";
else
temp <= temp(2 downto 0) & din;
end if;
else
temp <= temp;
end if;
out1 <= temp;
end process U1;

end behave;

library ieee;
use ieee.std_logic_1164.all;

entity mux4x1 is
port (
I : in std_logic_vector (3 downto 0);
sel : in std_logic_vector (1 downto 0);
out1 : out std_logic
);
end mux4x1;

architecture behavioural of mux4x1 is
begin
process (I, sel)
begin
case (sel) is
when "00" => out1 <= I(0);
when "01" => out1 <= I(1);
when "10" => out1 <= I(2);
when "11" => out1 <= I(3);
when others => out1 <= I(0);
end case;
end process;

end behavioural;

Add a comment
Know the answer?
Add Answer to:
Write a VHDL code using processes for the following logic circuit which include a shift register...
Your Answer:

Post as a guest

Your Name:

What's your source?

Earn Coins

Coins can be redeemed for fabulous gifts.

Not the answer you're looking for? Ask your own homework help question. Our experts will answer your question WITHIN MINUTES for Free.
Similar Homework Help Questions
  • Write a test bench for the following VHDL code -------------------------------------------------------------------------------------------------------------------------------- LIBRARY ieee ; USE ieee.std_logic_1164.all ;...

    Write a test bench for the following VHDL code -------------------------------------------------------------------------------------------------------------------------------- LIBRARY ieee ; USE ieee.std_logic_1164.all ; ENTITY registern IS GENERIC (N: INTEGER :=4);    -- INTEGER=32, 16, ….. PORT (D           : IN STD_LOGIC_VECTOR (N-1 downto 0); clk, reset, Load   : IN      STD_LOGIC ; Q           : OUT   STD_LOGIC_VECTOR (N-1 downto 0 )) ; END registern; ARCHITECTURE behavior OF registern IS BEGIN PROCESS (clk) BEGIN IF clk' EVENT AND clk='1' THEN IF (reset ='0') THEN    --synchronous reset Q<=(OTHERS=>’0’); ELSIF (L ='0') THEN Q<=D;...

  • QUESTION 1 Complete the following peice of VHDL code with the necessary VHDL statements for a...

    QUESTION 1 Complete the following peice of VHDL code with the necessary VHDL statements for a counter that counts through this sequence(0,9,17,15,4,26) repeatedly. library IEEE use IEEE.STD_LOGIC_1164 ALL entity GCC is Port ( systemClock, reset in STD_LOGIC end GCC architecture Behavioral of GCC is stateOutput out STD LOGIC_ VECTOR (4 downto 0)) component FreqDivider is Port (systemClock in STD_LOGIC; slowClock: out STD LOGIC); end component, signal nextState, presentState: std_logic_vector(5 downto 0) := "00000"; signal slowClock: std_logic begin FD0: FreqDivider port...

  • Draw the RTL schematic of the hardware that will be synthesized for the VHDL code below....

    Draw the RTL schematic of the hardware that will be synthesized for the VHDL code below. entity unknown is port (x: in std_logic_vector(7 downto 0); op: in std_logic_vector(1 downto 0); clk: in std_logic; f: out std_logic_vector(7 downto 0)); end entity. architecture arch of unknown is signal a, b, c, d: std_logic_vector(7 downto 0); begin d <= x; process (clk) begin if (rising_edge(clk)) then a <= b; b <= c + a; c <= d; if (op = “00”) then f...

  • in vhdl Manchester code is a coding scheme used to represent a bit in a data...

    in vhdl Manchester code is a coding scheme used to represent a bit in a data stream. A 'O' value of a bit is represented as a 0-to-1 transition in which the lead half is 'O' and the remaining half is '1'. Similarly, a '1' value of a bit is represented as a 1-to-transition, in which the lead half is 'l' and the remaining half is 0 For example, for the input string "110", the output is translated as: 110...

  • Please Write it in VHDL and complete the following code Create an entity called "regs" where...

    Please Write it in VHDL and complete the following code Create an entity called "regs" where you infer a true dual port (both ports can independently either read or write to any location) memory consisting of 32 16-bit words (64 Bytes). It should have the following black box interface and behavior: entity regs is port clk, en, rst in std_logic; İdl, İd2 : in std logic vector (4 downto 0); __ Addresses wr_enl, wr_ en2 in std logic dinl, din2...

  • 8.(5 points).There is an error in following VHDL code. Find the error and correct (only that...

    8.(5 points).There is an error in following VHDL code. Find the error and correct (only that line of code). LIBRARY ieee; USE ieee.std_logic_1164.all; ENTITY dec2to4 IS PORT (i IN STD LOGIC VECTOR (1 DOWNTO 0); : En IN STD_LOGIC; d OUT STD LOGIC); END dec2to4; ARCHITECTURE dataflow OF dec2to4 IS BEGIN SIGNAL Eni: STD_LOGIC_VECTOR(2 DOWNTO 0); Eni <= En & i; -concatenate signals WITH Eni SELECT d <"0001" WHEN "100" "0010" WHEN "101", "0100" WHEN "110", "1000" WHEN "111", 0000"...

  • Please fully answer BOTH parts of the question (a) and (b). a) Draw the high level...

    Please fully answer BOTH parts of the question (a) and (b). a) Draw the high level synthesized diagram of the following VHDL code. What does the following circuit do? Write the sequence of output generated by this circuit. library ieee; use ieee.std_logic_1164.all; entity sequence is port ( cout :out std_logic_vector (3 downto 0); clk :in std_logic; reset :in std_logic ); end entity; architecture rtl of sequence is signal count :std_logic_vector (3 downto 0); begin process (clk) begin if (rising_edge(clk)) then...

  • S2) Draw the logic circuit on the side of which the given VHDL code is real....

    S2) Draw the logic circuit on the side of which the given VHDL code is real. library IEEE; use IEEE.STD_LOGIC_1164.ALL; entity devre is 81: out STD_LOGIC; Y2 : out port (A,B,C : in STD_LOGIC; STD_LOGIC); end devre; architecture behavioral of devre is begin Y1 <= (A xor B) and (not C); Y2 <= (A and (B or C)); end behavioral;

  • 3. Study the VHDL code below for the multiplexer: -mux.vhd library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all;...

    3. Study the VHDL code below for the multiplexer: -mux.vhd library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; use jeee.std logic.arith.all; entity mux is port DIFF1, DIFF2: n std_logic_vector(4 downto O); ABSLT: out std_logic_vector(4 downto 0); CO: in std logic ); end mux; architecture behv of mux is begin with CO select ABSLT DIFF1 when o, a CO-0 selects B-A DIFF2 when 1',a Co-1 selects A-B "ZZZZZ" when others·.. high impedance otherwise end behy

  • (20 pts)VHDL. Implement the logic circuit specified in the following truth table by using a 4:1 m...

    (20 pts)VHDL. Implement the logic circuit specified in the following truth table by using a 4:1 mulitiplexer ome regular logic gates. 11 Draw a schematic of your implementation. 2) Suppose that you are given the following VHDL code of a 4:1 multiplexer. Please write a VHDL code to describe your implementation by using structure modeling technique, by using the following 4:1 multiplexer asia your answer component in your structure modeling. Note that you do not need to re-write the following...

ADVERTISEMENT
Free Homework Help App
Download From Google Play
Scan Your Homework
to Get Instant Free Answers
Need Online Homework Help?
Ask a Question
Get Answers For Free
Most questions answered within 3 hours.
ADVERTISEMENT
ADVERTISEMENT
ADVERTISEMENT