Question

Write a VHDL code using processes for the following logic circuit which include a shift register and 4x1 multiplexer. Use the entity below.             

entity registers_min_max is
port( din   : in std_logic_vector(3 downto 0);
      reset : in std_logic;
      clk   : in std_logic;
      sel   : in std_logic_vector(1 downto 0);
      reg_out : out std_logic_vector(3 downto 0));
end registers_min_max;

din reset RO clk reset R1 A C clk reset R2 clk reset R3 clk 3 0 sel LE

Answer 1

library ieee;
use ieee.std_logic_1164.all;

entity registers_min_max is
port( din : in std_logic; -- the din port is only single bit as in figure
reset : in std_logic;
clk : in std_logic;
sel : in std_logic_vector(1 downto 0);
LE : out std_logic; -- as LE is taken from the output of the mux as in figure//
out : out std_logic_vector(3 downto 0));
end registers_min_max;

architecture behave of register_min_max is
begin

shift1 : shift_register (clk => clk, reset => reset, din => din, out => temp );
mux : mux4x1 (in1 => temp, sel => sel, Y => LE);

out <= temp;

end behave;

library ieee;
use ieee.std_logic_1164.all;

entity shift_register is
port (
clk : in std_logic;
reset : in std_logic;
din : in std_logic;
out1 : out std_logic_vector(3 downto 0)
);
end shift_register;

architecture behave of shift_register is
signal temp : std_logic_vector (3 downto 0);
begin
U1:process (clk)
begin
if (clk'event and clk = '1') then
if (reset = '1') then
temp <= "0000";
else
temp <= temp(2 downto 0) & din;
end if;
else
temp <= temp;
end if;
out1 <= temp;
end process U1;

end behave;

library ieee;
use ieee.std_logic_1164.all;

entity mux4x1 is
port (
I : in std_logic_vector (3 downto 0);
sel : in std_logic_vector (1 downto 0);
out1 : out std_logic
);
end mux4x1;

architecture behavioural of mux4x1 is
begin
process (I, sel)
begin
case (sel) is
when "00" => out1 <= I(0);
when "01" => out1 <= I(1);
when "10" => out1 <= I(2);
when "11" => out1 <= I(3);
when others => out1 <= I(0);
end case;
end process;

end behavioural;