Question

Please Write it in VHDL and complete the following code

Create an entity called "regs" where you infer a true dual port (both ports can independently either read or write to any location) memory consisting of 32 16-bit words (64 Bytes). It should have the following black box interface and behavior: entity regs is port clk, en, rst in std_logic; İdl, İd2 : in std logic vector (4 downto 0); __ Addresses wr_enl, wr_ en2 in std logic dinl, din2 in std logic vector (15 downto 0) doutl, dout2 out std logic vector (15 downto 0) end regs; dout registers(idl) dout2 registers(id2) if reset is 1 registers(all) 0 else on every clock edge when enable is 1: registers(0) 0 if wr enl registers(idl) -dinl if wr en2 registers(id2) - din2

Answer 1

library ieee;

use ieee.std_logic_1164.all;

use ieee.numeric_std.all;

entity regs is

port ( clk, en, rst : in std_logic;

id1, id2 : in std_logic_vector (4 downto 0);

wr_en1, wr_en2 : in std_logic;

din1, din2 : in std_logic_vector (15 downto 0);

dout1, dout2 : out std_logic_vector (15 downto 0)

);

end regs;

architecture arch of regs is

type ram_memory is array (31 downto 0) of std_logic_vector (15 downto 0);

signal memory : ram_memory;

signal addr1, addr2 : std_logic_vector (4 downto 0);

begin

process (clk, rst)

begin

if (rst = '1') then

memory <= (others => (others => '0'));

elsif rising_edge (clk) then

if (en = '1') then

if (wr_en1 = '1') then

memory(to_integer(unsigned(id1))) <= din1;

end if;

if (wr_en2 = '1') then

memory(to_integer(unsigned(id2))) <= din2;

end if;

end if;

addr1 <= id1;

addr2 <= id2;

end if;

end process;

dout1 <= memory(to_integer(unsigned(addr1)));

dout2 <= memory(to_integer(unsigned(addr2)));

end arch;