Question

b. Suppose you are provided with a 4-bit ripple carry adder. It has the following entity declaration and schematic representation А(3:0] B[3: entity fourbit FA is portA, B in std logic_vector (3 downto 0); 4-bit RCA Cin in std_logic; S out stdlogic_vector (3 downto 0) Cout out std logic: Cin Cout S3:0] end fourbitFA Create a VHDL architecture for the following circuit (15 Marks) C3:0] D[3:0] A[3:0] B[3:0] Е[3:0] F[3:0] 4-bit RCA 4-bit RCA inA 4-bit RCA CinB CinC Coutl Sum2[3:0] Sum3[3:0] Out13:0 Out2[3:0] You may make use of the following template: entity adder circuit is in std logic_vector (3 downto 0) in std logic; out std logic_vector (3 downto 0) port A, B,C, D, E, F CinA, CinB, Cinc Out1, Out2 end adder circuit ARCHITECTURE behavior OF adder_circuit IS COMPONENT fourbit FA port A, B in std 1ogic_vector (3 downto 0); Cin in std_logic; S out std Iogic_vector (3 downto 0); Cout out std_logic; ) END COMPONENT: std_logic std logic_vector (3 downto 0); signal coutl signal sum2, sum3 You can add any of your own temporary signals here BEGIN You must complete the rest of this section END:

Answer 1

library ieee;
use ieee.std_logic_1164.all;

entity adder_circuit is
   port (   A, B, C, D, E, F   : in std_logic_vector(3 downto 0);
       Cin           : in std_logic;
       CinA, CinB, CinC   : in std_logic;
       Out1, Out2       : out std_logic_vector(3 downto 0)
   );
end adder_circuit;

ARCHITECTURE behavior OF adder_circuit IS

   COMPONENT fourbitFA
       port (   A, B   : in std_logic_vector(3 downto 0);
           Cin   : in std_logic;
           S   : out std_logic_vector(3 downto 0);
           Cout   : out std_logic
       );
   END COMPONENT;

   signal Cout1 : std_logic;
   signal sum2, sum3 : std_logic_vector(3 downto 0);

BEGIN

   UUT0 : fourbitFA port map (A, B, CinA, Out1, Cout1);
   UUT1 : fourbitFA port map (C, D, CinB, sum2, open);
   UUT2 : fourbitFA port map (E, F, CinC, sum3, open);
   Out2 <= sum3 when (Cout1 = '0') else sum2;

END;