Homework Answers
Add Answer to:
Answer the question below for the following code, What does reg (7:0) do? What does always...
3. Answer the question below for the following code. module Shift_Register8 (Q, Data_in, Clk, Load, Shift_left,...
3. Answer the question below for the following code. module Shift_Register8 (Q, Data_in, Clk, Load, Shift_left, Shift_right); output [ 7:0] Q; reg [7:0] Q; input [7:0] Data_in; input Clk, Load, Shift_left, Shift_right; always @ (posedge Clk) if (Load) Q<= Data_in; else case ( { Shift_left, Shift_right }) 2'600: if (Clk == 1) Q<=Q; 2'b01: if (Clk == 1) Q<= >> 1; 2'b10: if (Clk == 1) Q<=Q<< 1; default: Q<=Q; endcase endmodule a) What does reg (7:0] Q do? b)...
How do I create a testbench with the verilog code below? module ganada(Clk, U1, D2, U2,...
How do I create a testbench with the verilog code below? module ganada(Clk, U1, D2, U2, D3, U3, D4, F1, F2, F3, F4, CF, S); input Clk, U1, D2, U2, D3, U3, D4, F1, F2, F3, F4; output [6:0] CF, S; reg [6:0] CF, S; reg [1:0] SS, B, NS; initial begin NS=2'b00; SS=2'b00; end always@(posedge Clk) begin case(NS) 2'b00: CF=7'b1111001; 2'b01: CF=7'b0100100; 2'b10: CF=7'b0110000; 2'b11: CF=7'b0011001; endcase case(SUD) 2'b00: S=7'b1000000; 2'b01: S=7'b1111001; 2'b10: S=7'b0100100; default: S=7'b0000000; endcase if(U1==1 ||...
Given the following verilog code, draw the corresponding state diagram for it. module mysterious (input reset,...
Given the following verilog code, draw the corresponding state diagram for it. module mysterious (input reset, clk, TB, TA, output reg [1:0] LB, LA); reg [1:0] cstate, nstate; parameter S0 = 2'b00; parameter S1 = 2'b01; parameter S2 = 2'b10; parameter S3 = 2'b11; parameter grn = 2'b00; parameter ylw = 2'b01; parameter rd = 2'b10; // state register always @ (posedge clk, posedge reset) begin if (reset) cstate <= S0; else cstate <= nstate; end // next state logic...
Please explain what he verilog code does: module lab7_2_3( input clk, input Enable, input Clear, input...
Please explain what he verilog code does: module lab7_2_3( input clk, input Enable, input Clear, input Load, output [3:0] Q, reg [3:0] count, wire cnt_done ); assign cnt_done = ~| count; assign Q = count; always @(posedge clk) if (Clear) count <= 0; else if (Enable) if (Load | cnt_done) count <= 4'b1010; // decimal 10 else count <= count - 1; Endmodule
(15 pts) 1. Draw a logic diagram for the Verilog code. module Seq_Ckt ( CLK, PR,...
(15 pts) 1. Draw a logic diagram for the Verilog code. module Seq_Ckt ( CLK, PR, sel, Q); input CLK, PR, sel; output reg [2:0] Q; reg [2:0] y; assign Q = y; always @ (posedge PR, posedge CLK) begin if (PR== 1) then y <= 3'b111; else if (sel) begin y[2] <= y[1] ^ y[0]; y[1] <= y[2]; y[1]; end else y[2] <= y[2] ; y[1] <= y[1]; y[0]; y[O] <= y[0] <= end endmodule
2. What is wrong with the following code (More than one error may exist in each...
2. What is wrong with the following code (More than one error may exist in each seg module mux2_1 (10, 11, S, Y); input 10, 11, S; output Y; lalways @ (posedge s) begin if (S) Y=11; else Y=10; end endmodule module ESM (clk, a, outi, out2): input clk, a: output outi, outi: jalways @ (posedge clk) begin 1 if(state=0) begin if (a) state<=1; end 1 else begin if (-a) states : end end end Jalways @ (state) begin if...
why its 4-to-1 mux behavioral? What does the logic circuit represented by the following Verilog module...
why its 4-to-1 mux behavioral?
What does the logic circuit represented by the following Verilog module do, and what Verilog description style does it use? // My Verilog module #1 module mymodl ( x, d, q) input[1:0] x;input[3:0] d;output q; reg q; wire [1:0] x; wire [3:0] d; always ( x or d) begin case ( x ) 1 : q=d[1]; 2 : g=d[2]; 3 q d[3]; endcase end endmodule
Write a testbench for use in Quartus' ModelSim Altera in verilog for the following code of...
Write a testbench for use in Quartus' ModelSim Altera in verilog for the following code of a 4x16 register: module regFile4x16 (input clk, input write, input [2:0] wrAddr, input [15:0] wrData, input [2:0] rdAddrA, output [15:0] rdDataA, input [2:0] rdAddrB, output [15:0] rdDataB); reg [15:0] reg0, reg1, reg2, reg3; assign rdDataA = rdAddrA == 0 ? reg0 : rdAddrA == 1 ? reg1 : rdAddrA == 2 ? reg2 : rdAddrA == 3...
a Read the following codes in Verilog and the corresponding testbench file. Describe what the codes...
a Read the following codes in Verilog and the corresponding testbench file. Describe what the codes are doing by adding comments in the code. Then write down the simulation results of res1, res2, res3, and res4, respectively. Source code module vector_defn (num1, res1, res2, res3, res4); input [7:0] num1; output res1; output [3:0] res2; output [0:7] res3; output [15:0] res4; assign res1=num1[2]; assign res2=num1[7:4]; assign res3=num1; assign res4={2{num1}}; endmodule testbench: `timescale 1ns / 1ps module vector_defn_tb; reg [7:0] in1; wire...
Modify the Moore FSM below to detect the sequence "110" , simulate using the same test...
Modify the Moore FSM below to detect the sequence "110" , simulate using the same test bench and create a Moore Transition Diagram for the new sequence 110. module moore_seq ( input clock, reset, x, output reg z ); //assign binary encoded codes to the states A through D parameter A = 2'b00, B = 2'b01, C = 2'b10, D = 2'b11; reg [1 : 0] current_state, next_state; //Section 1: Next state generator (NSG)...
3. Answer the question below for the following code. module Shift_Register8 (Q, Data_in, Clk, Load, Shift_left, Shift_right); output [ 7:0] Q; reg [7:0] Q; input [7:0] Data_in; input Clk, Load, Shift_left, Shift_right; always @ (posedge Clk) if (Load) Q<= Data_in; else case ( { Shift_left, Shift_right }) 2'600: if (Clk == 1) Q<=Q; 2'b01: if (Clk == 1) Q<= >> 1; 2'b10: if (Clk == 1) Q<=Q<< 1; default: Q<=Q; endcase endmodule a) What does reg (7:0] Q do? b)...
(15 pts) 1. Draw a logic diagram for the Verilog code. module Seq_Ckt ( CLK, PR, sel, Q); input CLK, PR, sel; output reg [2:0] Q; reg [2:0] y; assign Q = y; always @ (posedge PR, posedge CLK) begin if (PR== 1) then y <= 3'b111; else if (sel) begin y[2] <= y[1] ^ y[0]; y[1] <= y[2]; y[1]; end else y[2] <= y[2] ; y[1] <= y[1]; y[0]; y[O] <= y[0] <= end endmodule
2. What is wrong with the following code (More than one error may exist in each seg module mux2_1 (10, 11, S, Y); input 10, 11, S; output Y; lalways @ (posedge s) begin if (S) Y=11; else Y=10; end endmodule module ESM (clk, a, outi, out2): input clk, a: output outi, outi: jalways @ (posedge clk) begin 1 if(state=0) begin if (a) state<=1; end 1 else begin if (-a) states : end end end Jalways @ (state) begin if...
why its 4-to-1 mux behavioral?
What does the logic circuit represented by the following Verilog module do, and what Verilog description style does it use? // My Verilog module #1 module mymodl ( x, d, q) input[1:0] x;input[3:0] d;output q; reg q; wire [1:0] x; wire [3:0] d; always ( x or d) begin case ( x ) 1 : q=d[1]; 2 : g=d[2]; 3 q d[3]; endcase end endmodule
Most questions answered within 3 hours.
-
SQL help:
Design a database diagram for a database that stores information
about the Downloads that...
asked 57 minutes ago -
In 1970s and 1980s, molecular biologists discovered that the
hormone testosterone, binds a receptor protein that...
asked 3 hours ago -
january 1 2010 road catering service purchase a piece of
equipment for 58000 which is expected...
asked 3 hours ago -
Explain Mertons concept of anomie is and what the
modes of adaptation to it are?
asked 4 hours ago -
Jamie is doing a survey at her school about whether the students
feel the cafeteria food...
asked 5 hours ago -
How many liters of 0.669 M KOH will be needed to raise the pH of
0.339...
asked 8 hours ago -
A liquid of density 1270 kg/m 3 flows steadily through a pipe of
varying diameter and...
asked 8 hours ago -
Questions: What should the American executive do?
'A visiting American executive finds that a foreign subsidiary...
asked 8 hours ago -
Activity based costing was introduced as an alternative to
absorption costing.
1. Discuss using illustration the...
asked 8 hours ago -
1. You own shares of Crane DVD Company and are interested in
selling them. With so...
asked 8 hours ago -
How many grams of He are necessary to fill a balloon having a
volume of 4.5E3...
asked 8 hours ago -
The 2 patients, still in the hospital, were interviewed by a
MoH epidemiologist. The interviews revealed...
asked 8 hours ago