Question

a Read the following codes in Verilog and the corresponding testbench file. Describe what the codes are doing by adding comments in the code. Then write down the simulation results of res1, res2, res3, and res4, respectively.

Source code

module vector_defn (num1, res1, res2, res3, res4);

input [7:0] num1;

output res1;

output [3:0] res2;

output [0:7] res3;

output [15:0] res4;

assign res1=num1[2];

assign res2=num1[7:4];

assign res3=num1;

assign res4={2{num1}};

endmodule

testbench:

`timescale 1ns / 1ps

module vector_defn_tb;

reg [7:0] in1;

wire out1;

wire [3:0] out2;

wire [0:7] out3;

wire [15:0] out4;

vector_defn UUT(.num1(in1),.res1(out1),.res2(out2),.res3(out3));

initial begin

in1 = 8’hEC;

#100;

end

endmodule

b. the following code describes a 3-bit shift register.

module register(

input [2:0] R,

input Load,

input Clock,

output reg [2:0] Q);

always@ (posedge Clock)

     if (Load)

             Q <= R;

     else

             Q <= {Q[0], Q[1] ^ Q[2], Q[2]};

endmodule

If 001 is loaded into the shift register initially, what is the sequence of numbers generated? List the binary numbers it generates, starting from 001.